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path: root/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
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* [mips] Set HWEncoding field of registers. Use delete functionAkira Hatanaka2012-12-101-2/+2
| | | | | | getMipsRegisterNumbering and use MCRegisterInfo::getEncodingValue instead. llvm-svn: 169760
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-5/+5
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* [mips] Delete MipsFunctionInfo::EmitNOAT. Unconditionally print directiveAkira Hatanaka2012-11-021-5/+2
| | | | | | | "set .noat" so that the assembler doesn't issue warnings when register $AT is used. llvm-svn: 167310
* Move TargetData to DataLayout.Micah Villmow2012-10-081-1/+1
| | | | llvm-svn: 165402
* The mips 64bit instructions DSLL, DSRA, DSRL, DEXT and DINS get transformed ↵Jack Carter2012-10-021-17/+0
| | | | | | | | | | | | by the assembler or through codegen direct object output to other variants based on the value of the immediate values of the operands. If the code is generated as assembler, this transformation does not occur assuming that it will occur later in the assembler. This code was originally called from MipsAsmPrinter.cpp and we needed to check for OutStreamer.hasRawTextSupport(). This was not a good place for it and has been moved to MCTargetDesc/MipsMCCodeEmitter.cpp where both direct object and the assembler use it it automagically. The test cases have been checked in for a number of weeks now. llvm-svn: 165067
* MIPS DSP: add code necessary for pseudo instruction lowering.Akira Hatanaka2012-09-271-0/+11
| | | | llvm-svn: 164747
* Remove redundant semicolons which are null statements.Dmitri Gribenko2012-09-101-1/+1
| | | | llvm-svn: 163547
* There are some Mips instructions that are lowered by the Jack Carter2012-09-061-25/+9
| | | | | | | | | | | | | | | | assembler such as shifts greater than 32. In the case of direct object, the code gen needs to do this lowering since the assembler is not involved. With the advent of the llvm-mc assembler, it also needs to do the same lowering. This patch makes that specific lowering code accessible to both the direct object output and the assembler. This patch does not affect generated output. llvm-svn: 163287
* The instruction DINS may be transformed into DINSU or DEXTM dependingJack Carter2012-08-311-3/+3
| | | | | | | | | | | | | | | | | | | | | on the size of the extraction and its position in the 64 bit word. This patch allows support of the dext transformations with mips64 direct object output. 0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32 DINS The field is entirely contained in the right-most word of the doubleword 32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64 DINSM The field straddles the words of the doubleword 32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32 DINSU The field is entirely contained in the left-most word of the doubleword llvm-svn: 163010
* The instruction DEXT may be transformed into DEXTU or DEXTM dependingJack Carter2012-08-281-0/+11
| | | | | | | | | | | | | | | | | | | | | on the size of the extraction and its position in the 64 bit word. This patch allows support of the dext transformations with mips64 direct object output. 0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32 DINS The field is entirely contained in the right-most word of the doubleword 32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64 DINSM The field straddles the words of the doubleword 32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32 DINSU The field is entirely contained in the left-most word of the doubleword llvm-svn: 162782
* Some instructions are passed to the assembler to beJack Carter2012-08-281-20/+24
| | | | | | | | | | | | | transformed to the final instruction variant. An example would be dsrll which is transformed into dsll32 if the shift value is greater than 32. For direct object output we need to do this transformation in the codegen. If the instruction was inside branch delay slot, it was being missed. This patch corrects this oversight. llvm-svn: 162779
* Mips specific inline asm operand modifier 'M':Jack Carter2012-07-181-3/+8
| | | | | | | | | | | | | | | | | | | | | | Print the high order register of a double word register operand. In 32 bit mode, a 64 bit double word integer will be represented by 2 32 bit registers. This modifier causes the high order register to be used in the asm expression. It is useful if you are using doubles in assembler and continue to control register to variable relationships. This patch also fixes a related bug in a previous patch: case 'D': // Second part of a double word register operand case 'L': // Low order register of a double word register operand case 'M': // High order register of a double word register operand I got 'D' and 'M' confused. The second part of a double word operand will only match 'M' for one of the endianesses. I had 'L' and 'D' be the opposite twins when 'L' and 'M' are. llvm-svn: 160429
* Doubleword Shift Left Logical Plus 32Jack Carter2012-07-161-1/+21
| | | | | | | | | | | | | | | | | | | | | Mips shift instructions DSLL, DSRL and DSRA are transformed into DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between 32 and 63 Here is a description of DSLL: Purpose: Doubleword Shift Left Logical Plus 32 To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits Description: GPR[rd] <- GPR[rt] << (sa+32) The 64-bit doubleword contents of GPR rt are shifted left, inserting zeros into the emptied bits; the result is placed in GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa. This patch implements the direct object output of these instructions. llvm-svn: 160277
* This change removes an "initialization" warning.Jack Carter2012-07-111-4/+3
| | | | | | | | Even though variable in question could not be initialized before use, the code was such that the compiler had no way of knowing that. llvm-svn: 160081
* Mips specific inline asm operand modifier 'L'.Jack Carter2012-07-101-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Low order register of a double word register operand. Operands are defined by the name of the variable they are marked with in the inline assembler code. This is a way to specify that the operand just refers to the low order register for that variable. It is the opposite of modifier 'D' which specifies the high order register. Example: main() { long long ll_input = 0x1111222233334444LL; long long ll_val = 3; int i_result = 0; __asm__ __volatile__( "or %0, %L1, %2" : "=r" (i_result) : "r" (ll_input), "r" (ll_val)); } Which results in: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -8 addu $2, $2, $25 sw $2, 0($sp) lui $2, 13107 ori $3, $2, 17476 <-- Low 32 bits of ll_input lui $2, 4369 ori $4, $2, 8738 <-- High 32 bits of ll_input addiu $5, $zero, 3 <-- Low 32 bits of ll_val addiu $2, $zero, 0 <-- High 32 bits of ll_val #APP or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val #NO_APP addiu $sp, $sp, 8 jr $ra If not direction is done for the long long for 32 bit variables results in using the low 32 bits as ll_val shows. There is an existing bug if 'L' or 'D' is used for the destination register for 32 bit long longs in that the target value will be updated incorrectly for the non-specified part unless explicitly set within the inline asm code. llvm-svn: 160028
* Changes per review of commit 159787Jack Carter2012-07-061-6/+5
| | | | | | | | | | Mips specific inline asm operand modifier D. Comment changes and predicate change. llvm-svn: 159802
* Mips specific inline asm operand modifier D.Jack Carter2012-07-051-7/+41
| | | | | | | | | | | | Print the second half of a double word operand. The include list was cleaned up a bit as well. Also the test case was modified to test for both big and little patterns. llvm-svn: 159787
* Changed the formatting sequence of a curly brace to Jack Carter2012-06-281-2/+2
| | | | | | the comment per code review feedback. llvm-svn: 159376
* The Mips specific inline asm operand modifier 'z' has theJack Carter2012-06-281-1/+13
| | | | | | | | following description in the gnu sources: Print $0 if operand is zero otherwise print the op normally. llvm-svn: 159324
* Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp andBill Wendling2012-06-281-3/+3
| | | | | | | | | include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h. The reasoning is because the DebugInfo module is simply an interface to the debug info MDNodes and has nothing to do with analysis. llvm-svn: 159312
* The inline asm operand modifier 'c' is suppose Jack Carter2012-06-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to be generic across architectures. It has the following description in the gnu sources: Substitute immediate value without immediate syntax Several Architectures such as x86 have local implementations of operand modifier 'c' which go beyond the above description slightly. To make use of the generic modifiers without overriding local implementation one can make a call to the base class method for AsmPrinter::PrintAsmOperand() in the locally derived method's "default" case in the switch statement. That way if it is already defined locally the generic version will never get called. This change is needed when test/CodeGen/generic/asm-large-immediate.ll failed on a native Mips board. The test was assuming a generic implementation was in place. Affected files: lib/Target/Mips/MipsAsmPrinter.cpp: Changed the default case to call the base method. lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Added 'c' to the switch cases. test/CodeGen/Mips/asm-large-immediate.ll Mips compiled version of the generic one Contributer: Jack Carter llvm-svn: 158925
* Fix coding style violations. Remove white spaces and tabs.Akira Hatanaka2012-06-141-2/+2
| | | | llvm-svn: 158471
* Remove code in MipsAsmPrinter and MipsMCInstLower.Akira Hatanaka2012-06-141-9/+0
| | | | llvm-svn: 158434
* Bundle jump/branch instructions with the instructions in the delay slot inAkira Hatanaka2012-06-131-3/+8
| | | | | | | | | delay slot filler pass of MIPS, per suggestion of Jakob Stoklund Olesen. This change, along with the fix in r158154, enables machine verification to be run after delay slot filling. llvm-svn: 158426
* disable use of directive .set nomicromipsAkira Hatanaka2012-06-131-1/+2
| | | | | | | | until this directive is pushed in gas to open source fsf Patch by Reed Kotler. llvm-svn: 158381
* Remove code which is no longer needed in MipsAsmPrinter and MipsMCInstLower.Akira Hatanaka2012-06-021-57/+0
| | | | llvm-svn: 157867
* Add support for the mips inline asm 'm' output modifier.Eric Christopher2012-05-301-0/+5
| | | | | | Patch by Jack Carter. llvm-svn: 157709
* Remove the code that emits MIPS' .cprestore directive.Akira Hatanaka2012-05-251-22/+0
| | | | llvm-svn: 157493
* Turn on mips16 pseudo op when compiling for mips16.Akira Hatanaka2012-05-241-1/+7
| | | | | | | | Expand test case for this. Patch by Reed Kotler. llvm-svn: 157410
* Add support for the 'd' mips inline asm output modifier.Eric Christopher2012-05-191-12/+17
| | | | | | Patch by Jack Carter. llvm-svn: 157093
* Add support for the mips 'x' inline asm modifier.Eric Christopher2012-05-181-0/+5
| | | | | | Patch by Jack Carter. llvm-svn: 157057
* Make the following changes in MipsAsmPrinter.cpp:Akira Hatanaka2012-05-121-20/+5
| | | | | | | | | - Remove code which lowers pseudo SETGP01. - Fix LowerSETGP01. The first two of the three instructions that are emitted to initialize the global pointer register now use register $2. - Stop emitting .cpload directive. llvm-svn: 156689
* Add support for the 'X' inline asm operand modifier.Eric Christopher2012-05-101-4/+16
| | | | | | Patch by Jack Carter. llvm-svn: 156577
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-5/+5
| | | | | | since they are equivalent. llvm-svn: 155188
* Emit all directives except for ".cprestore" during asm printing rather than emitAkira Hatanaka2012-03-281-45/+92
| | | | | | | | | | | | | | | | them as machine instructions. Directives ".set noat" and ".set at" are now emitted only at the beginning and end of a function except in the case where they are emitted to enclose .cpload with an immediate operand that doesn't fit in 16-bit field or unaligned load/stores. Also, make the following changes: - Remove function isUnalignedLoadStore and use a switch-case statement to determine whether an instruction is an unaligned load or store. - Define helper function CreateMCInst which generates an instance of an MCInst from an opcode and a list of operands. llvm-svn: 153552
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-1/+1
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Remove unused header files.Akira Hatanaka2012-03-091-2/+0
| | | | llvm-svn: 152447
* remove blanks, and some code formatJia Liu2012-02-281-9/+9
| | | | llvm-svn: 151625
* Add an option to use a virtual register as the global base register instead ofAkira Hatanaka2012-02-241-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... llvm-svn: 151402
* Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles2012-02-191-4/+1
| | | | llvm-svn: 150918
* remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.Jia Liu2012-02-171-1/+1
| | | | llvm-svn: 150805
* add Emacs tag and fix some comment error in file headersJia Liu2012-02-171-1/+1
| | | | llvm-svn: 150775
* Cleanup Mips code and rename some variables. Patch by Jack CarterBruno Cardoso Lopes2011-12-301-5/+5
| | | | llvm-svn: 147383
* Detect unaligned loads/stores that have been added for Mips64 support.Akira Hatanaka2011-12-241-1/+8
| | | | llvm-svn: 147234
* Tidy up. Simplify logic. No functional change intended.Akira Hatanaka2011-12-191-1/+2
| | | | llvm-svn: 146896
* Expand .cprestore directive to multiple instructions if the offset does not fit Akira Hatanaka2011-12-131-9/+7
| | | | | | in a 16-bit field. llvm-svn: 146469
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-2/+2
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* This patch makes the following changes necessary for MIPS' direct code emission.Akira Hatanaka2011-11-231-9/+16
| | | | | | | | - lower unaligned loads/stores. - encode the size operand of instructions INS and EXT. - emit relocation information needed for JAL (jump-and-link). llvm-svn: 145113
* Remove MipsMCSymbolRefExpr.Akira Hatanaka2011-11-151-1/+0
| | | | llvm-svn: 144654
* Mips MC object code emission improvements:Bruno Cardoso Lopes2011-11-111-0/+1
| | | | | | | | | | "With this patch we can now generate runnable Mips code through LLVM direct object emission. We have run numerous simple programs, both C and C++ and with -O0 and -O3 from the output. The code is not production ready, but quite useful for experimentation." Patch and message by Jack Carter llvm-svn: 144414
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