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path: root/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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* When Mips16 frames grow large, the immediate field may exceed the maximumReed Kotler2013-02-081-2/+11
| | | | | | | | allowed size for the instruction. This code uses RegScavenger to fix this. We sometimes need 2 registers for Mips16 so we must handle things differently than how register scavenger is normally used. llvm-svn: 174696
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-3/+3
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Call llvm_unreachable instead of assert.Reed Kotler2012-12-211-1/+1
| | | | llvm-svn: 170822
* There is one more patch to finish large frames. Make sure we assertReed Kotler2012-12-201-0/+4
| | | | | | on code that has large frames which will not yet compile correctly. llvm-svn: 170673
* Turn on register scavenger for Mips 16Reed Kotler2012-12-201-0/+26
| | | | | | | We use an unused Mips 32 register for the emergency slot instead of using the stack. llvm-svn: 170665
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-13/+13
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Implement ADJCALLSTACKUP and ADJCALLSTACKDOWNReed Kotler2012-10-311-3/+17
| | | | llvm-svn: 167107
* This patch is for the implementation of mips16 complex pattern addr16.Reed Kotler2012-10-281-37/+46
| | | | | | | | | | | | | | | | | | | | | Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll. The Mips16InstrInfo.td has been updated to use addr16 instead of addr. The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues. llvm-svn: 166897
* Delete member MipsFunctionInfo::OutArgFIRange and code that accesses it.Akira Hatanaka2012-09-261-9/+3
| | | | llvm-svn: 164718
* Remove unused private field to silence build warning.Craig Topper2012-08-231-3/+2
| | | | llvm-svn: 162426
* Add a member of type Mips16InstrInfo/MipsSEInstrInfo to classAkira Hatanaka2012-08-221-2/+2
| | | | | | | | Mips16RegisterInfo/MipsSERegisterInfo. No changes in functionality. llvm-svn: 162413
* 1. Redo mips16 instructions to avoid multiple opcodes for same instruction.Akira Hatanaka2012-08-031-0/+53
| | | | | | | | | Change these to patterns. 2. Add another 16 instructions. Patch by Reed Kotler. llvm-svn: 161272
* Implement MipsSERegisterInfo::eliminateCallFramePseudoInstr. The function emitsAkira Hatanaka2012-07-311-0/+9
| | | | | | | instructions that decrement and increment the stack pointer before and after a call when the function does not have a reserved call frame. llvm-svn: 161093
* Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo andAkira Hatanaka2012-07-311-0/+49
MipsSERegisterInfo. llvm-svn: 161092
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