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* [mips] Add definition of instruction "drotr32" (double rotate right plus 32).Akira Hatanaka2013-09-071-0/+4
| | | | llvm-svn: 190232
* Changed commentJack Carter2013-08-271-1/+1
| | | | llvm-svn: 189396
* [Mips] Support for unaligned load/store microMips instructionsJack Carter2013-08-131-0/+16
| | | | | | | | This includes instructions lwl, lwr, swl and swr. Patch by Zoran Jovnovic llvm-svn: 188312
* Mips ELF: MicroMips direct object Little endian support. Jack Carter2013-08-081-4/+15
| | | | | | | | Test included. Patch by Zoran Jovanovich llvm-svn: 188024
* Mips ELF: Mark object file as ABI compliant Jack Carter2013-06-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When producing objects that are abi compliant we are marking neither the object file nor the assembly file correctly and thus generate warnings. We need to set the EF_CPIC flag in the ELF header when generating direct object. Note that the warning is only generated when compiling without PIC. When compiling with clang the warning will be suppressed by supplying: -Wa,-mno-shared -Wa,-call_nonpic Also the following directive should also be added: .option pic0 when compiling without PIC, This eliminates the need for supplying: -mno-shared -call_nonpic on the assembler command line. Patch by Douglas Gilmore llvm-svn: 184220
* Use pointers to the MCAsmInfo and MCRegInfo.Bill Wendling2013-06-181-1/+1
| | | | | | | | | Someone may want to do something crazy, like replace these objects if they change or something. No functionality change intended. llvm-svn: 184175
* Make helper functions static.Rafael Espindola2013-05-274-113/+65
| | | | | | And remove header and cpp file that are empty after that. llvm-svn: 182746
* Remove the MachineMove class.Rafael Espindola2013-05-131-4/+4
| | | | | | | | | | | | It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. llvm-svn: 181680
* Remove unused argument.Rafael Espindola2013-05-103-5/+4
| | | | llvm-svn: 181618
* [mips] First patch which adds support for micromips.Akira Hatanaka2013-04-191-1/+14
| | | | | | | | | This patch adds support for recoded (meaning assembly-language compatible to standard mips32) arithmetic 32-bit instructions. Patch by Zoran Jovanovic. llvm-svn: 179873
* Mips assembler: Enable handling of nested expressionsJack Carter2013-04-171-25/+37
| | | | | | | | | | This patch allows the Mips assembler to parse and emit nested expressions as instruction operands. It also extends the expansion of memory instructions when an offset is given as an expression. Contributer: Vladimir Medic llvm-svn: 179657
* Fix the invalid opcode for Mips branch instructions in the assemblerJack Carter2013-03-221-4/+6
| | | | | | | | | | | | | | | For mips a branch an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. Previously, the code generator did not perform the shift of the immediate branch offset which resulted in wrong instruction opcode. This patch fixes the issue. Contributor: Vladimir Medic llvm-svn: 177687
* Fix the (clang -Werror) build by removing an unused member variable.David Blaikie2013-02-201-2/+1
| | | | llvm-svn: 175607
* ELF symbol table field st_other support, Jack Carter2013-02-191-0/+4
| | | | | | | | | | | | excluding visibility bits. Mips (o32 abi) specific e_header setting. EF_MIPS_ABI_O32 needs to be set in the ELF header flags for o32 abi output. Contributer: Reed Kotler llvm-svn: 175569
* ELF symbol table field st_other support, Jack Carter2013-02-191-1/+4
| | | | | | | | | | | | excluding visibility bits. Mips (Mips16) specific e_header setting. EF_MIPS_ARCH_ASE_M16 needs to be set in the ELF header flags for Mips16. Contributer: Reed Kotler llvm-svn: 175566
* ELF symbol table field st_other support, Jack Carter2013-02-193-6/+30
| | | | | | | | | | | excluding visibility bits. Mips (MicroMips) specific STO handling . The st_other field settig for STO_MIPS_MICROMIPS Contributer: Zoran Jovanovic llvm-svn: 175564
* Remove a final dependency on the form field in tablegen; which is a remnantReed Kotler2013-02-151-6/+0
| | | | | | | of the old jit and which we don't intend to support in mips16 or micromips. This dependency is for the testing of whether an instruction is a pseudo. llvm-svn: 175297
* This patch that sets the Mips ELF header flag for Jack Carter2013-02-051-0/+3
| | | | | | | | MicroMips architectures. Contributer: Zoran Jovanovic llvm-svn: 174360
* This patch changes a static_cast to dyn_castJack Carter2013-02-051-1/+5
| | | | | | | | for MipsELFStreamer objects. Contributer: Jack Carter llvm-svn: 174354
* Removing initializer for the field removed in r173887David Blaikie2013-01-301-1/+1
| | | | llvm-svn: 173888
* Remove unused variable (introduced in r173884) to clear clang -Werror buildDavid Blaikie2013-01-301-2/+0
| | | | llvm-svn: 173887
* Forgot to add new file to CMakeListsJack Carter2013-01-301-0/+1
| | | | llvm-svn: 173886
* This patch implements runtime Mips specificJack Carter2013-01-303-1/+100
| | | | | | | | setting of ELF header e_flags. Contributer: Jack Carter llvm-svn: 173884
* This patch reworks how llvm targets set Jack Carter2013-01-301-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | and update ELF header e_flags. Currently gathering information such as symbol, section and data is done by collecting it in an MCAssembler object. From MCAssembler and MCAsmLayout objects ELFObjectWriter::WriteObject() forms and streams out the ELF object file. This patch just adds a few members to the MCAssember class to store and access the e_flag settings. It allows for runtime additions to the e_flag by assembler directives. The standalone assembler can get to MCAssembler from getParser().getStreamer().getAssembler(). This patch is the generic infrastructure and will be followed by patches for ARM and Mips for their target specific use. Contributer: Jack Carter llvm-svn: 173882
* Clean up assignment of CalleeSaveStackSlotSize: get rid of the default and ↵Eli Bendersky2013-01-231-2/+3
| | | | | | explicitly set this in every target that needs to change it from the default. llvm-svn: 173270
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-183-0/+112
| | | | | | | | | | | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Support for Mips register information sections. Mips ELF object files have a section that is dedicated to register use info. Some of this information such as the assumed Global Pointer value is used by the linker in relocation resolution. The register info file is .reginfo in o32 and .MIPS.options in 64 and n32 abi files. This patch contains the changes needed to create the sections, but leaves the actual register accounting for a future patch. Contributer: Jack Carter llvm-svn: 172847
* This patch fixes a Mips specific bug where Jack Carter2013-01-151-1/+7
| | | | | | | | | | | we need to generate a N64 compound relocation R_MIPS_GPREL_32/R_MIPS_64/R_MIPS_NONE. The bug was exposed by the SingleSourcetest case DuffsDevice.c. Contributer: Jack Carter llvm-svn: 172496
* This patch produces the correct addend value forJack Carter2013-01-081-0/+1
| | | | | | | | an R_MIPS_GPREL16 relocation. Contributer: Jack Carter llvm-svn: 171882
* This patch produces the correct pointer size Jack Carter2013-01-081-0/+4
| | | | | | | | | | | | value in the 64 bit .eh_frame section. It doesn't however allow exception handling to work yet since it depends on the correct relocation model being set in the ELF header flags. Contributer: Jack Carter llvm-svn: 171881
* Renamed MCInstFragment to MCRelaxableFragment and added some comments.Eli Bendersky2013-01-081-1/+1
| | | | | | No change in functionality. llvm-svn: 171822
* This patch is needed to make c++ exceptions work for mips16.Reed Kotler2012-12-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mips16 is really a processor decoding mode (ala thumb 1) and in the same program, mips16 and mips32 functions can exist and can call each other. If a jal type instruction encounters an address with the lower bit set, then the processor switches to mips16 mode (if it is not already in it). If the lower bit is not set, then it switches to mips32 mode. The linker knows which functions are mips16 and which are mips32. When relocation is performed on code labels, this lower order bit is set if the code label is a mips16 code label. In general this works just fine, however when creating exception handling tables and dwarf, there are cases where you don't want this lower order bit added in. This has been traditionally distinguished in gas assembly source by using a different syntax for the label. lab1: ; this will cause the lower order bit to be added lab2=. ; this will not cause the lower order bit to be added In some cases, it does not matter because in dwarf and debug tables the difference of two labels is used and in that case the lower order bits subtract each other out. To fix this, I have added to mcstreamer the notion of a debuglabel. The default is for label and debug label to be the same. So calling EmitLabel and EmitDebugLabel produce the same result. For various reasons, there is only one set of labels that needs to be modified for the mips exceptions to work. These are the "$eh_func_beginXXX" labels. Mips overrides the debug label suffix from ":" to "=." . This initial patch fixes exceptions. More changes most likely will be needed to DwarfCFException to make all of this work for actual debugging. These changes will be to emit debug labels in some places where a simple label is emitted now. Some historical discussion on this from gcc can be found at: http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00623.html http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01273.html llvm-svn: 170279
* [mips] Set HWEncoding field of registers. Use delete functionAkira Hatanaka2012-12-102-98/+7
| | | | | | getMipsRegisterNumbering and use MCRegisterInfo::getEncodingValue instead. llvm-svn: 169760
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-2/+2
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Mips direct object xgot supportJack Carter2012-11-214-1/+45
| | | | | | | | | | | | | | This patch provides support for the MIPS relocations: *) R_MIPS_GOT_HI16 *) R_MIPS_GOT_LO16 *) R_MIPS_CALL_HI16 *) R_MIPS_CALL_LO16 These are used for large GOT instruction sequences. Contributer: Jack Carter llvm-svn: 168471
* [mips] Add target operand flag enums for big GOT relocations.Akira Hatanaka2012-11-211-1/+7
| | | | llvm-svn: 168450
* This patch moves from using a hard coded number (4) Jack Carter2012-10-031-2/+4
| | | | | | | | | | | | | for the number of bytes in a particular instruction to using const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode()); Desc.getSize() This is necessary with the advent of 16 bit instructions with mips16 and micromips. It is also puts Mips in compliance with the other targets for getting instruction size. llvm-svn: 165171
* The mips 64bit instructions DSLL, DSRA, DSRL, DEXT and DINS get transformed ↵Jack Carter2012-10-024-4/+134
| | | | | | | | | | | | by the assembler or through codegen direct object output to other variants based on the value of the immediate values of the operands. If the code is generated as assembler, this transformation does not occur assuming that it will occur later in the assembler. This code was originally called from MipsAsmPrinter.cpp and we needed to check for OutStreamer.hasRawTextSupport(). This was not a good place for it and has been moved to MCTargetDesc/MipsMCCodeEmitter.cpp where both direct object and the assembler use it it automagically. The test cases have been checked in for a number of weeks now. llvm-svn: 165067
* Add case clauses for returning dsp accumulator encoding values in functionAkira Hatanaka2012-09-261-2/+4
| | | | | | getMipsRegisterNumbering. llvm-svn: 164720
* When creating MCAsmBackend pass the CPU string as well. In X86AsmBackendRoman Divacky2012-09-182-8/+16
| | | | | | | | | store this and use it to not emit long nops when the CPU is geode which doesnt support them. Fixes PR11212. llvm-svn: 164132
* Remove unused private fields to silence -Wunused-private-field.Craig Topper2012-09-151-9/+6
| | | | llvm-svn: 163973
* Fix Doxygen issues:Dmitri Gribenko2012-09-141-1/+1
| | | | | | | | | | * wrap code blocks in \code ... \endcode; * refer to parameter names in paragraphs correctly (\arg is not what most people want -- it starts a new paragraph); * use \param instead of \arg to document parameters in order to be consistent with the rest of the codebase. llvm-svn: 163902
* Fix a couple of Doxygen comment issues pointed out by -Wdocumentation.Dmitri Gribenko2012-09-121-1/+1
| | | | llvm-svn: 163721
* The Mips standalone assembler fpu instruction support.Jack Carter2012-09-071-1/+1
| | | | | | | Test cases included Contributer: Vladimir Medic llvm-svn: 163363
* Mips specific llvm assembler support for branch and jump instructions.Jack Carter2012-09-061-2/+9
| | | | | | | Test case included. Contributer: Vladimir Medic llvm-svn: 163277
* For mips64 switch statements in subroutines could generate Jack Carter2012-08-221-1/+1
| | | | | | | | | | | | | within the codegen EK_GPRel64BlockAddress. This was not supported for direct object output and resulted in an assertion. This change adds support for EK_GPRel64BlockAddress for direct object. One fallout from this is to turn on rela relocations for mips64 to match gas. llvm-svn: 162334
* Correct MCJIT functionality for MIPS32 architecture.Akira Hatanaka2012-08-171-3/+5
| | | | | | | | | | No new tests are added. All tests in ExecutionEngine/MCJIT that have been failing pass after this patch is applied (when "make check" is done on a mips board). Patch by Petar Jovanovic. llvm-svn: 162135
* Mips relocation R_MIPS_64 relocates a 64 bit double word.Jack Carter2012-08-072-0/+4
| | | | | | | | I hit this in a very large program (spirit.cpp), but have not figured out how to make a small make check test for it. llvm-svn: 161366
* Mips relocations R_MIPS_HIGHER and R_MIPS_HIGHEST.Jack Carter2012-08-064-2/+30
| | | | | | | | | | | | | | These 2 relocations gain access to the highest and the second highest 16 bits of a 64 bit object. R_MIPS_HIGHER %higher(A+S) The %higher(x) function is [ (((long long) x + 0x80008000LL) >> 32) & 0xffff ]. R_MIPS_HIGHEST %highest(A+S) The %highest(x) function is [ (((long long) x + 0x800080008000LL) >> 48) & 0xffff ]. llvm-svn: 161348
* Add comment for relocations MO_HIGHER and HIGHEST in MipsBaseInfo.h.Akira Hatanaka2012-07-231-0/+2
| | | | llvm-svn: 160636
* Add HIGHER and HIGHEST relocations to Mips backend.Akira Hatanaka2012-07-211-1/+4
| | | | llvm-svn: 160599
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