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* [mips][ias] Implement one N32 case (of two) for .cpsetup.Daniel Sanders2016-06-141-28/+27
| | | | | | | | | | | | | | | | | | | | | | This patch implements the N32 case where -mno-shared is in effect. The case where -mshared is in effect will be added later since doing that now requires additional changes to how we handle %hi(%neg(%gp_rel(foo))) expressions to emit the three relocations as three relocations (currently only one of the three would be emitted) which then requires further changes to our MCFixup handling. While we could fix both cases together, fixing the -mno-shared case allows us to fix the ELFCLASS bug (where N32 incorrectly uses ELFCLASS64 instead of ELFCLASS32) in a way that allows cpsetup.s to check for a correct output instead of another incorrect output. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D21131 llvm-svn: 272652
* Move instances of std::function.Benjamin Kramer2016-06-121-4/+4
| | | | | | Or replace with llvm::function_ref if it's never stored. NFC intended. llvm-svn: 272513
* [mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructionsHrvoje Varga2016-06-092-0/+37
| | | | | | Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
* [mips] EABI CodeGen is completely untested and seems to have bitrotted. ↵Daniel Sanders2016-06-032-6/+2
| | | | | | | | | | | | | | | | | | Remove it. Summary: There are no tests*, no EABI buildbots, and simple test cases do not work. * There is a single MIPS16 test using a mips*-gnueabi triple but this test doesn't test EABI and the triple doesn't cause EABI to be used. Reviewers: sdardis Subscribers: tberghammer, danalbert, srhines, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20906 llvm-svn: 271658
* [mips] Implement 'la' macro in PIC mode for O32.Daniel Sanders2016-06-032-0/+5
| | | | | | | | | | | | | | | | Summary: N32 support will follow in a later patch since the symbol version of 'la' incorrectly believes N32 to have 64-bit pointers and rejects it early. This fixes the three incorrectly expanded 'la' macros found in bionic. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D20820 llvm-svn: 271644
* [mips] Enforce compact branch register restrictionsSimon Dardis2016-05-311-4/+12
| | | | | | | | | | | | | | | Enforce compact branch register restrictions such as the use of the zero register, both operands being the same register. Emit clear error in such cases as the issue is subtle. For bovc and bnvc, silently fixup such cases when emitting objects directly, like LLVM started doing in rL269899. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D20475 llvm-svn: 271301
* ps][microMIPS] Add R_MICROMIPS_PC21_S1 relocationZoran Jovanovic2016-05-194-3/+21
| | | | | | Differential Revision: http://reviews.llvm.org/D15526 llvm-svn: 270048
* Delete Reloc::Default.Rafael Espindola2016-05-181-2/+0
| | | | | | | | | | | | Having an enum member named Default is quite confusing: Is it distinct from the others? This patch removes that member and instead uses Optional<Reloc> in places where we have a user input that still hasn't been maped to the default value, which is now clear has no be one of the remaining 3 options. llvm-svn: 269988
* Don't pass a Reloc::Model to MC.Rafael Espindola2016-05-181-1/+1
| | | | | | | | | | | | MC only needs to know if the output is PIC or not. It never has to decide about creating GOTs and PLTs for example. The only thing that MC itself uses this information for is expanding "macros" in sparc and mips. The rest I am pretty sure could be moved to CodeGen. This is a cleanup and isolates the code from future changes to Reloc::Model. llvm-svn: 269909
* [PATCH] [mips] Restrict the creation of compact branchesSimon Dardis2016-05-182-0/+27
| | | | | | | | | | | | | | | | | Restrict the creation of compact branches so that they do meet the ISA requirements. Notably do not permit $zero to be used as a operand for compact branches and ensure that some other branches fulfil the requirement that rs != rt. Fixup cases where $rs > $rt for bnec and beqc. Recommit of rL269893 with reviewers comments. Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D20284 llvm-svn: 269899
* Revert "[mips] Restrict the creation of compact branches"Simon Dardis2016-05-182-27/+0
| | | | | | | | This reverts commit rL269893. Incorrect patch applied. llvm-svn: 269897
* [mips] Restrict the creation of compact branchesSimon Dardis2016-05-182-0/+27
| | | | | | | | | | | | | | | Restrict the creation of compact branches so that they meet the ISA encoding requirements. Notably do not permit $zero to be used as a operand for compact branches and ensure that some other branches fulfil the requirement that rs != rt. Fixup cases where $rs > $rt for bnec and beqc. Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D20284 llvm-svn: 269893
* [mips][microMIPS] Implement BEQZC and BNEZC instructionsZoran Jovanovic2016-05-172-0/+27
| | | | | | Differential Revision: http://reviews.llvm.org/D15417 llvm-svn: 269755
* [mips][ias] Fix R_MICROMIPS_GOT16 evaluation and eliminate symbol for ↵Daniel Sanders2016-05-162-7/+4
| | | | | | | | | | | | | | | | | | | R_MICROMIPS_(GOT|HI|LO)16 Summary: The failure r269410 worked around turned out to be caused by an incorrect evaluation of R_MICROMIPS_GOT16 which then caused the GOT entries to be incorrect. This patch fixes the evaluation and reverts r269410. Reviewers: sdardis, vkalintiris, rafael Subscribers: rafael, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20242 llvm-svn: 269641
* [mips][ias] EF_MIPS_MICROMIPS should iff microMIPS code was emitted.Daniel Sanders2016-05-161-5/+8
| | | | | | | | | | | | | | | Summary: This fixes PR27682. Additionally, '.set micromips' by itself is not sufficient to raise the EF_MIPS_MICROMIPS flag. It is also necessary to emit a microMIPS instruction. This has also been fixed. Reviewers: sdardis, vkalintiris, rafael Subscribers: rafael, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20214 llvm-svn: 269639
* [mips] Enable IAS by default for 32-bit MIPS targets (O32).Daniel Sanders2016-05-141-0/+5
| | | | | | | | | | | | | | | | | | | Summary: The MIPS IAS can now pass 'ninja check-all', recurse, build a bootable linux kernel, and pass a variety of LNT testing. Unfortunately we can't enable it by default for 64-bit targets yet since the N32 ABI is still very buggy and this also means we can't enable it for N64 either because we can't distinguish between N32 and N64 in the relevant code. Reviewers: vkalintiris Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D18759 Differential Revision: http://reviews.llvm.org/D18761 llvm-svn: 269560
* [mips][ias] Work around yet another incorrect microMIPS relocation ↵Daniel Sanders2016-05-131-3/+7
| | | | | | | | | | | | evaluation exposed by r268900. It's not entirely clear why R_MICROMIPS_(GOT|HI16|LO16) are evaluated incorrectly in a small number of the LNT tests at this point. However, it's not related to the STO_MIPS_MICROMIPS issue. At this point all the microMIPS-related changes of r268900 have been reverted. llvm-svn: 269410
* [mips][microMIPS] Implement APPEND, BPOSGE32C, MODSUB, MULSA.W.PH and ↵Hrvoje Varga2016-05-132-0/+30
| | | | | | | | MULSAQ_S.W.PH instructions Differential Revision: http://reviews.llvm.org/D14117 llvm-svn: 269408
* [mips][ias] Fix O32 .cprestore directive when inside .set noat region and ↵Daniel Sanders2016-05-121-6/+7
| | | | | | | | | | | | | | | | | | offset is in range. Summary: This expands on r269179 to fix an additional case that was not covered by our tests. The assembler temporary is not needed when the .cprestore offset fits inside a simm16 and it is not an error to use it inside a '.set noat' in this case. Reviewers: emaste, seanbruno, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20199 llvm-svn: 269295
* [mips][ias] Work around incorrect another microMIPS relocation evaluation ↵Daniel Sanders2016-05-121-1/+1
| | | | | | | | | | | | | | | | | | | | exposed by r268900 As explained in r269196, microMIPS has a special case that is not correctly implemented in LLVM. If we have a symbol 'foo' which is equivalent to '.text+0x10'. The value of an R_MICROMIPS_LO16 relocation using 'foo' is 'foo+0x11' and not 'foo+0x10'. The in-place addend should therefore be 0x11. This commit reverts a little more of the effect of r268900 by keeping the symbol when the STO_MIPS_MICROMIPS flag is set for R_MIPS_GPREL32 relocations. This fixes SingleSource/UnitTests/2003-08-11-VaListArg, and SingleSource/UnitTests/2003-05-07-VarArgs for microMIPS. I believe there are additional relocations that have the same issue (e.g. R_MIPS_64, and R_MIPS_GPREL16) but for now I'm focusing on restoring our internal buildbots back to the green state we had in r268899. llvm-svn: 269294
* Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions"Hrvoje Varga2016-05-122-16/+0
| | | | | | This reverts commit r269176 as it caused test-suite failure. llvm-svn: 269287
* [mips][ias] Correct ELF eflags when Octeon is the target.Daniel Sanders2016-05-123-15/+28
| | | | | | | | | | Reviewers: sdardis Subscribers: petarj, mpf, dsanders, spetrovic, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D18899 llvm-svn: 269283
* [mips][ias] Handle N64 compound relocations and R_MIPS_SUB in ↵Daniel Sanders2016-05-121-5/+6
| | | | | | | | | | | | | | | | | | | needsRelocateWithSymbol() Summary: This eliminates the default case for N64 that was left out of r269047. The change to R_MIPS_SUB is needed in this patch to make this testable since %lo(%neg(%gp_rel(foo))) and %hi(%neg(%gp_rel(foo))) remain the only ways to get a compound relocation from the assembler. Reviewers: sdardis, rafael Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D20097 llvm-svn: 269280
* [mips][ias] Work around incorrect microMIPS relocation evaluation exposed by ↵Daniel Sanders2016-05-111-0/+5
| | | | | | | | | | | | | | | r268900 microMIPS has a special case that is not correctly implemented in LLVM. If we have a symbol 'foo' which is equivalent to '.text+0x10'. The value of an R_MICROMIPS_LO16 relocation using 'foo' is 'foo+0x11' and not 'foo+0x10'. The in-place addend should therefore be 0x11. Work around this by partially reverting the effect of r268900 by keeping the symbol when the STO_MIPS_MICROMIPS flag is set. This fixes SingleSource/Regression/C/PR640 for microMIPS. llvm-svn: 269196
* [mips][ias] Fix N32 and N64 .cprestore directive when inside .set noat region.Daniel Sanders2016-05-111-12/+19
| | | | | | | | | | | | | | | | | | Summary: r268058 unintentionally made the retrieval of the current assembler temporary unconditional. This was fine for the existing tests but it broke the cases where the assembler temporary is not needed (N32/N64 or not PIC) and is unavailable due to a '.set noat' directive. This fixes FreeBSD's libc. Reviewers: emaste, sdardis, seanbruno Subscribers: dsanders, emaste, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20093 llvm-svn: 269179
* [mips][microMIPS] Implement CFC*, CTC* and LDC* instructionsHrvoje Varga2016-05-112-0/+16
| | | | | | Differential Revision: http://reviews.llvm.org/D19713 llvm-svn: 269176
* [mips][ias] Make the default path unreachable in needsRelocateWithSymbol() ↵Daniel Sanders2016-05-101-1/+114
| | | | | | | | | | | | | | | (except for N64). Following post-commit comments on r268900 from Rafael Espindola: The missing relocations are now explicitly listed in the switch statement with appropriate FIXME comments and the default path is now unreachable. The temporary exception to this is that compound relocations for N64 still have a default path that returns true. This is because fixing that case ought to be a separate patch. Also make R_MIPS_NONE return false since it has no effect on the section data. llvm-svn: 269047
* [mips] Try to fix 'truncation from FindBestPredicateResult to bool' reported ↵Daniel Sanders2016-05-091-3/+3
| | | | | | by MSVC llvm-svn: 268928
* [mips][ias] R_MIPS_(GOT|HI|LO|PC)16 and R_MIPS_GPREL32 do not need symbols.Daniel Sanders2016-05-091-11/+10
| | | | | | | | | | | | | | | | | Summary: In theory, care must be taken to ensure that pairs of R_MIPS_(GOT|HI|LO)16 make the same decision on both relocs in the reloc pair but in practice this isn't as hard as it sounds and only limits the complexity of the predicate used. We handle all three with the same code to ensure their decisions always agree with each other. Reviewers: sdardis Subscribers: rafael, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19016 llvm-svn: 268900
* MipsELFObjectWriter.cpp: Activate debug printer just for +Asserts. ↵NAKAMURA Takumi2016-05-071-0/+2
| | | | | | [-Wunused-function] llvm-svn: 268848
* [mips] Fix inconsistent .cprestore behaviour between direct object emission ↵Daniel Sanders2016-05-061-0/+8
| | | | | | | | | | | | | | | | | | | and assembling. Summary: Direct object emission has an initialization order problem where an InitMCObjectFile is called after MipsTargetELFStreamer determines whether PIC is enabled by default or not. There doesn't seem to be point that initializes all cases so split the responsibility between MipsTargetELFStreamer and MipsAsmPrinter. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19728 llvm-svn: 268737
* [mips] Correct the ordering of HI/LO pairs in the relocation table.Daniel Sanders2016-05-061-186/+269
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: There seems to have been a misunderstanding as to the meaning of 'offset' in the rules laid down by our ABI. The previous code believed that 'offset' meant the offset within the section that the relocation is applied to. However, it should have meant the offset from the symbol used in the relocation expression. This patch adds two fields to ELFRelocationEntry and uses them to correct the order of relocations for MIPS. These fields contain: * The original symbol before shouldRelocateWithSymbol() is considered. This ensures that R_MIPS_GOT16 is able to correctly distinguish between local and external symbols, allowing us to tell whether %got() requires a matching %lo() or not (local symbols require one, external symbols don't). It also prevents confusing cases where the fuzzy matching rules cause things like %hi(foo)/%lo(foo+3) and %hi(bar)/%lo(bar+1) to swap their %lo()'s. * The original offset before shouldRelocateWithSymbol() is considered. The existing Addend field is always zero when the object uses in place addends (because it's already moved it to the encoding) but MIPS needs to use the original offset to ensure that the linker correctly calculates the carry-in bit for %hi() and %got(). IAS ensures that unmatchable %hi()/%got() relocations are placed at the end of the table to ensure that the linker rejects the table (we're unable to report such errors directly). The alternatives to this risk accidental matching against inappropriate relocations which may silently compute incorrect values due to an incorrect carry bit between the %lo() and %hi()/%got(). Reviewers: sdardis Subscribers: dsanders, sdardis, rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D19718 llvm-svn: 268733
* [mips][ias] Only round section sizes when explicitly requested.Daniel Sanders2016-05-041-12/+24
| | | | | | | | As requested by Rafael Espindola in his post-commit comments on r268036. This makes the previous behaviour the default while still allowing verification of IAS. llvm-svn: 268496
* [mips] Use MipsMCExpr instead of MCSymbolRefExpr for all relocations.Daniel Sanders2016-05-038-187/+408
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is much closer to the way MIPS relocation expressions work (%hi(foo + 2) rather than %hi(foo) + 2) and removes the need for the various bodges in MipsAsmParser::evaluateRelocExpr(). Removing those bodges ensures that the constant stored in MCValue is the full 32 or 64-bit (depending on ABI) offset from the symbol. This will be used to correct the %hi/%lo matching needed to sort the relocation table correctly. As part of this: * Gave MCExpr::print() the ability to omit parenthesis when emitting a symbol reference inside a MipsMCExpr operator like %hi(X). Without this we print things like %lo(($L1)). * %hi(%neg(%gprel(X))) is now three MipsMCExpr's instead of one. Most of the related special cases have been removed or moved to MipsMCExpr. We can remove the rest as we gain support for the less common relocations when they are not part of this specific combination. * Renamed MipsMCExpr::VariantKind and the enum prefix ('VK_') to avoid confusion with MCSymbolRefExpr::VariantKind and its prefix (also 'VK_'). * fixup_Mips_GOT_Local and fixup_Mips_GOT_Global were found to be identical and merged into fixup_Mips_GOT. * MO_GOT16 and MO_GOT turned out to be identical and have been merged into MO_GOT. * VK_Mips_GOT and VK_Mips_GOT16 turned out to be the same thing so they have been merged into MEK_GOT Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19716 llvm-svn: 268379
* [mips][ias] Move createCpRestoreMemOp to MipsTargetStreamer. NFC.Daniel Sanders2016-04-291-16/+36
| | | | | | | | | | | | | | | Summary: This removes the temporary call to isIntegratedAssemblerRequired() which was added recently. It's effect is now acheived directly in the MipsTargetStreamer hierarchy. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19715 llvm-svn: 268058
* [mips][ias] Split expandMemInst between MipsAsmParser and ↵Daniel Sanders2016-04-291-0/+100
| | | | | | | | | | | | | | | | | | | | | | MipsTargetStreamer. Almost NFC. Summary: The portion in MipsAsmParser is responsible for figuring out which expansion to use, while the portion in MipsTargetStreamer is responsible for emitting it. This allows us to remove the call to isIntegratedAssemblerRequired() which is currently ensuring the effect of .cprestore only occurs when writing objects. The small functional change is that the memory offsets are now correctly printed as signed values. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19714 llvm-svn: 268042
* [mips][ias] Moved most instruction emission helpers to MipsTargetStreamer. NFC.Daniel Sanders2016-04-291-0/+93
| | | | | | | | | | | | | | | | | | | Summary: * Moved all the emit*() helpers to MipsTargetStreamer. * Moved createNop() to MipsTargetStreamer as emitNop() and emitEmptyDelaySlot(). This instruction has been split to distinguish between the 'nop' instruction and the nop used in delay slots which is sometimes a different nop to the 'nop' instruction (e.g. for short delay slots on microMIPS). * Moved createAddu() to MipsTargetStreamer as emitAddu(). * Moved createAppropriateDSLL() to MipsTargetStreamer as emitDSLL(). Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19712 llvm-svn: 268041
* [mips][ias] Make section sizes a multiple of the alignment.Daniel Sanders2016-04-291-0/+15
| | | | | | | | | | Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19008 llvm-svn: 268036
* [mips][atomics] Fix partword atomic binary operation implementationSimon Dardis2016-04-282-0/+5
| | | | | | | | | | | | | | | Currently Mips::emitAtomicBinaryPartword() does not properly respect the width of pointers. For MIPS64 this causes the memory address that the ll/sc sequence uses to be truncated. At runtime this causes a segmentation fault. This can be fixed by applying similar changes as r266204, so that a full 64bit pointer is loaded. Reviewers: dsanders Differential Review: http://reviews.llvm.org/D19651 llvm-svn: 267900
* [mips][microMIPS] Revert commit r266861.Zoran Jovanovic2016-04-222-16/+0
| | | | | | Commit r266861 was the reason for failing tests in LLVM test suite. llvm-svn: 267166
* [mips][microMIPS] Add R_MICROMIPS_PC18_S3 relocationZoran Jovanovic2016-04-224-2/+23
| | | | | | Differential Revision: http://reviews.llvm.org/D15026 llvm-svn: 267130
* [mips][microMIPS] Add R_MICROMIPS_PC19_S2 relocationZoran Jovanovic2016-04-214-2/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D14915 llvm-svn: 266988
* [mips][microMIPS] Add R_MICROMIPS_PC26_S1 relocationZoran Jovanovic2016-04-214-1/+24
| | | | | | Differential Revision: http://reviews.llvm.org/D14822 llvm-svn: 266985
* [mips][microMIPS]Implement CFC*, CTC* and LDC* instructionsHrvoje Varga2016-04-202-0/+16
| | | | | | Differential Revision: http://reviews.llvm.org/D18640 llvm-svn: 266861
* [mips][ias] Stream macro expansions to output instead of buffering them. NFC.Daniel Sanders2016-04-181-10/+7
| | | | | | | | | | | | | | | | | | | Summary: This will allows us to eliminate some magic numbers from the offset operand of branch instructions in favour of symbols and makes it possible to avoid double-filling delay slots when clang is given -save-temps. parseDirectiveCpRestore() is calling isIntegratedAssemblerRequired() for the moment since correctly pushing the generation of these instructions into the ELF target streamer is tricky enough to warrant a separate patch. Reviewers: sdardis, vkalintiris Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19164 llvm-svn: 266602
* [NFC] Header cleanupMehdi Amini2016-04-184-6/+3
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* [mips] Make Static a default relocation model for MIPS codegenPetar Jovanovic2016-04-111-3/+1
| | | | | | | | | | | | This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
* [mips] Split mem_msa into range checked mem_simm10 and mem_simm10_lsl[123]Daniel Sanders2016-03-312-49/+9
| | | | | | | | | | | | | | Summary: Also, made test_mi10.s formatting consistent with the majority of the MC tests. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18435 llvm-svn: 265014
* [MC][mips] Add MipsMCInstrAnalysis class and register it as MC instruction ↵Simon Atanasyan2016-03-241-0/+36
| | | | | | | | | | | | | analyzer The `MipsMCInstrAnalysis` class overrides the `evaluateBranch` method and calculates target addresses for branch and calls instructions. That allows llvm-objdump to print functions' names in branch instructions in the disassemble mode. Differential Revision: http://reviews.llvm.org/D18209 llvm-svn: 264309
* [mips] MIPS32R6 compact branch supportDaniel Sanders2016-03-141-1/+6
| | | | | | | | | | | | | | | | | | | | | | | Summary: MIPSR6 introduces a class of branches called compact branches. Unlike the traditional MIPS branches which have a delay slot, compact branches do not have a delay slot. The instruction following the compact branch is only executed if the branch is not taken and must not be a branch. It works by generating compact branches for MIPS32R6 when the delay slot filler cannot fill a delay slot. Then, inspecting the generated code for forbidden slot hazards (a compact branch with an adjacent branch or other CTI) and inserting nops to clear this hazard. Patch by Simon Dardis. Reviewers: vkalintiris, dsanders Subscribers: MatzeB, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16353 llvm-svn: 263444
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