| Commit message (Collapse) | Author | Age | Files | Lines |
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Implement microMIPS 16-bit unconditional branch instruction B.
Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1
Differential Revision: http://reviews.llvm.org/D3514
llvm-svn: 226657
|
| |
|
|
| |
llvm-svn: 226595
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Implement microMIPS 16-bit unconditional branch instruction B.
Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1
Differential Revision: http://reviews.llvm.org/D3514
llvm-svn: 226577
|
| |
|
|
|
|
| |
into the assert.
llvm-svn: 225160
|
| |
|
|
|
|
| |
Differential Revision: http://reviews.llvm.org/D5667
llvm-svn: 224338
|
| |
|
|
|
|
| |
Differential Revision: http://reviews.llvm.org/D5579
llvm-svn: 222901
|
| |
|
|
|
|
| |
Differential Revision: http://reviews.llvm.org/D5519
llvm-svn: 222367
|
| |
|
|
|
|
|
|
|
|
| |
Add header guards to files that were missing guards. Remove #endif comments
as they don't seem common in LLVM (we can easily add them back if we decide
they're useful)
Changes made by clang-tidy with minor tweaks.
llvm-svn: 215558
|
| |
|
|
|
|
| |
Differential Revision: http://reviews.llvm.org/D3860
llvm-svn: 209659
|
| |
|
|
| |
llvm-svn: 208607
|
| |
|
|
|
|
| |
'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition
llvm-svn: 207506
|
| |
|
|
|
|
|
| |
definition below all of the header #include lines, lib/Target/...
edition.
llvm-svn: 206842
|
| |
|
|
|
|
| |
There's a couple additional bits I missed.
llvm-svn: 205195
|
| |
|
|
| |
llvm-svn: 205194
|
| |
|
|
| |
llvm-svn: 202811
|
| |
|
|
|
|
|
|
|
|
|
| |
Patch implements %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions for MIPS
by creating target expression class MipsMCExpr.
Patch by Sasa Stankovic.
Differential Revision: http://llvm-reviews.chandlerc.com/D2592
llvm-svn: 200783
|
| |
|
|
| |
llvm-svn: 196999
|
| |
|
|
|
|
| |
here is to make save/restore into variable number of argument instructions.
llvm-svn: 196726
|
| |
|
|
|
|
|
|
|
| |
CommonTableGen.
add_public_tablegen_target adds *CommonTableGen to LLVM_COMMON_DEPENDS.
LLVM_COMMON_DEPENDS affects add_llvm_library (and other add_target stuff) within its scope.
llvm-svn: 195927
|
| |
|
|
|
|
| |
sets them.
llvm-svn: 195921
|
| |
|
|
|
|
|
|
| |
intrinsics)
Updated some of the vshf since they (correctly) emit splati's now
llvm-svn: 191511
|
| |
|
|
| |
llvm-svn: 191302
|
| |
|
|
| |
llvm-svn: 190234
|
| |
|
|
|
|
|
|
| |
which is
equivalent to "beq $zero, $zero, offset".
llvm-svn: 190220
|
| |
|
|
| |
llvm-svn: 188851
|
| |
|
|
|
|
| |
EmitAlias flag and have MipsInstPrinter::printAlias print the aliases.
llvm-svn: 187824
|
| |
|
|
|
|
|
| |
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.
llvm-svn: 187821
|
| |
|
|
|
|
| |
turns "bal" into "bgezal".
llvm-svn: 187440
|
| |
|
|
| |
llvm-svn: 187371
|
| |
|
|
|
|
| |
operands.
llvm-svn: 187238
|
| |
|
|
|
|
|
|
| |
needed. The generic method printOperand will do.
No functionality change.
llvm-svn: 187231
|
| |
|
|
|
|
|
|
|
|
| |
instructions "beqz", "bnez" and "move", when possible.
beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or $2, $3, $zero => move $2, $3
llvm-svn: 187229
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
and enables the instruction printer to print aliased
instructions.
Due to usage of RegisterOperands a change in common
code (utils/TableGen/AsmWriterEmitter.cpp) is required
to get the correct register value if it is a RegisterOperand.
Contributer: Vladimir Medic
llvm-svn: 174358
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
register names in the standalone assembler llvm-mc.
Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.
The problem is resolved by the Mips specific AsmParser
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.
Contributer: Vladimir Medic
llvm-svn: 172284
|
| |
|
|
| |
llvm-svn: 169819
|
| |
|
|
| |
llvm-svn: 169724
|
| |
|
|
| |
llvm-svn: 168460
|
| |
|
|
| |
llvm-svn: 160599
|
| |
|
|
|
|
| |
mips32 rev1 (the directives are emitted when target is mips32r2 too).
llvm-svn: 159770
|
| |
|
|
| |
llvm-svn: 157885
|
| |
|
|
|
|
|
|
| |
MCInstPrinter.
All implementations used the same code.
llvm-svn: 153866
|
| |
|
|
|
|
| |
using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations.
llvm-svn: 153863
|
| |
|
|
|
|
| |
getInstructionName and the static data it contains since the same tables are already in MCInstrInfo.
llvm-svn: 153860
|
| |
|
|
|
|
|
| |
Used to allow context sensitive printing of super-register or sub-register
references.
llvm-svn: 152043
|
| |
|
|
| |
llvm-svn: 151625
|
| |
|
|
| |
llvm-svn: 151332
|
| |
|
|
| |
llvm-svn: 150805
|
| |
|
|
| |
llvm-svn: 150775
|
| |
|
|
| |
llvm-svn: 149961
|
| |
|
|
| |
llvm-svn: 146896
|