| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | [mips][ias] Range check uimm2 operands and fix a bug this revealed. | Daniel Sanders | 2015-11-06 | 1 | -12/+9 |
| * | [mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI a... | Hrvoje Varga | 2015-10-28 | 1 | -0/+20 |
| * | [mips][microMIPS] Implement LB, LBE, LBU and LBUE instructions | Hrvoje Varga | 2015-10-16 | 1 | -0/+46 |
| * | [mips][microMIPS] Implement LLE and SCE instructions | Hrvoje Varga | 2015-10-15 | 1 | -0/+3 |
| * | [mips][microMIPS] Fix an invalid read for lwm32 and reserved reglist values. | Daniel Sanders | 2015-09-18 | 1 | -0/+6 |
| * | [mips][microMIPS] Fix an issue with disassembling lwm32 instruction | Zoran Jovanovic | 2015-09-15 | 1 | -1/+1 |
| * | [mips] Added support for various EVA ASE instructions. | Daniel Sanders | 2015-09-15 | 1 | -12/+37 |
| * | [mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL... | Zoran Jovanovic | 2015-09-09 | 1 | -0/+13 |
| * | [mips][microMIPS] Implement CACHEE and PREFE instructions | Zoran Jovanovic | 2015-09-09 | 1 | -0/+22 |
| * | [mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions | Zoran Jovanovic | 2015-09-08 | 1 | -0/+23 |
| * | [mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions | Zoran Jovanovic | 2015-09-07 | 1 | -6/+22 |
| * | [mips][microMIPS] Implement SW and SWE instructions | Zoran Jovanovic | 2015-08-18 | 1 | -0/+23 |
| * | [mips][microMIPS] Create microMIPS64r6 subtarget and implement DALIGN, DAUI, ... | Zoran Jovanovic | 2015-08-12 | 1 | -1/+2 |
| * | [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. | Daniel Sanders | 2015-06-27 | 1 | -0/+17 |
| * | [mips] Fix some UB by shifting before sign-extending | Justin Bogner | 2015-06-23 | 1 | -1/+1 |
| * | [mips] Add new format for dmtc2/dmfc2 for Octeon CPUs. | Kai Nacke | 2015-05-28 | 1 | -0/+12 |
| * | Use std::bitset for SubtargetFeatures. | Michael Kuperstein | 2015-05-26 | 1 | -5/+5 |
| * | MC: Modernize MCOperand API naming. NFC. | Jim Grosbach | 2015-05-13 | 1 | -146/+146 |
| * | Reverting r237234, "Use std::bitset for SubtargetFeatures" | Michael Kuperstein | 2015-05-13 | 1 | -5/+5 |
| * | Use std::bitset for SubtargetFeatures | Michael Kuperstein | 2015-05-13 | 1 | -5/+5 |
| * | [mips][microMIPSr6] Implement disassembler support | Jozef Kolek | 2015-04-20 | 1 | -4/+11 |
| * | Revert "Use std::bitset for SubtargetFeatures" | Michael Kuperstein | 2015-03-24 | 1 | -5/+5 |
| * | Use std::bitset for SubtargetFeatures | Michael Kuperstein | 2015-03-24 | 1 | -5/+5 |
| * | Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures. | Michael Kuperstein | 2015-02-19 | 1 | -5/+5 |
| * | Use std::bitset for SubtargetFeatures | Michael Kuperstein | 2015-02-19 | 1 | -5/+5 |
| * | [mips] Merge disassemblers into a single implementation. | Daniel Sanders | 2015-02-11 | 1 | -84/+18 |
| * | [mips][microMIPS] Implement movep instruction | Zoran Jovanovic | 2015-02-10 | 1 | -0/+65 |
| * | [mips][microMIPS] Fix disassembling of 16-bit microMIPS instructions LWM16 an... | Jozef Kolek | 2015-02-10 | 1 | -7/+23 |
| * | [Mips][Disassembler] When disassembler meets cache/pref instructions for r6 i... | Vladimir Medic | 2015-01-29 | 1 | -0/+22 |
| * | [mips][microMIPS] Implement LWGP instruction | Jozef Kolek | 2015-01-28 | 1 | -0/+21 |
| * | [mips] fix spelling of 'disassembler' | Alexei Starovoitov | 2015-01-23 | 1 | -3/+3 |
| * | [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B | Jozef Kolek | 2015-01-21 | 1 | -0/+16 |
| * | [mips][microMIPS] Implement ADDIUPC instruction | Jozef Kolek | 2015-01-21 | 1 | -0/+9 |
| * | [Mips][Disassembler]When disassembler meets load/store from coprocessor 2 ins... | Vladimir Medic | 2015-01-21 | 1 | -0/+21 |
| * | Reverted revision 226577. | Jozef Kolek | 2015-01-20 | 1 | -16/+0 |
| * | [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B | Jozef Kolek | 2015-01-20 | 1 | -0/+16 |
| * | [mips][microMIPS] Implement BEQZ16 and BNEZ16 instructions | Jozef Kolek | 2015-01-12 | 1 | -0/+16 |
| * | [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions | Jozef Kolek | 2014-12-23 | 1 | -0/+22 |
| * | [mips][microMIPS] Implement LWSP and SWSP instructions | Jozef Kolek | 2014-12-23 | 1 | -0/+21 |
| * | Fix UBSan bootstrap: replace shift of negative value with multiplication. | Alexey Samsonov | 2014-12-23 | 1 | -1/+1 |
| * | The single check for N64 inside MipsDisassemblerBase's subclasses is actually... | Vladimir Medic | 2014-12-16 | 1 | -4/+4 |
| * | [mips][microMIPS] Implement SWP and LWP instructions | Zoran Jovanovic | 2014-12-16 | 1 | -0/+3 |
| * | Add disassembler tests for mips3 platform. There are no functional changes. | Vladimir Medic | 2014-12-15 | 1 | -1/+2 |
| * | The andi16, addiusp and jraddiusp micromips instructions were missing dedicat... | Vladimir Medic | 2014-12-01 | 1 | -0/+39 |
| * | [mips][microMIPS] Implement SWM16 and LWM16 instructions | Zoran Jovanovic | 2014-11-27 | 1 | -0/+24 |
| * | [mips] Add synci instruction. | Daniel Sanders | 2014-11-27 | 1 | -0/+20 |
| * | [mips][microMIPS] Implement disassembler support for 16-bit instructions LI16... | Jozef Kolek | 2014-11-27 | 1 | -0/+60 |
| * | [mips][microMIPS] Implement disassembler support for 16-bit instructions LBU1... | Jozef Kolek | 2014-11-26 | 1 | -1/+62 |
| * | [mips][microMIPS] Implement 16-bit instructions registers including ZERO inst... | Jozef Kolek | 2014-11-24 | 1 | -0/+12 |
| * | [mips][microMIPS] Implement disassembler support for 16-bit instructions | Jozef Kolek | 2014-11-24 | 1 | -11/+54 |
