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* [mips] Emit .reloc R_{MICRO}MIPS_JALR along with j(al)r(c) $25Vladimir Stefanovic2019-01-171-4/+1
| | | | | | | | | | | | The callee address is added as an optional operand (MCSymbol) in AdjustInstrPostInstrSelection() and then used by asm printer to insert: '.reloc tmplabel, R_MIPS_JALR, symbol tmplabel:'. Controlled with '-mips-jalr-reloc', default is true. Differential revision: https://reviews.llvm.org/D56694 llvm-svn: 351485
* [mips][micrompis] Emit 16bit NOPs by defaultAleksandar Beserminji2019-01-091-5/+14
| | | | | | | | | Emit 16bit NOPs by default. Use 32bit NOPs in delay slots where necessary. Differential https://reviews.llvm.org/D55323 llvm-svn: 350733
* [mips][mc] Emit R_{MICRO}MIPS_JALR when expanding jal to jalrVladimir Stefanovic2018-12-101-3/+21
| | | | | | | | | | | When replacing jal with jalr, also emit '.reloc R_MIPS_JALR' (R_MICROMIPS_JALR for micromips). The linker might then be able to turn jalr into a direct call. Add '-mips-jalr-reloc' to enable/disable this feature (default is true). Differential revision: https://reviews.llvm.org/D55292 llvm-svn: 348760
* Fix clang -Wimplicit-fallthrough warnings across llvm, NFCReid Kleckner2018-11-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch should not introduce any behavior changes. It consists of mostly one of two changes: 1. Replacing fall through comments with the LLVM_FALLTHROUGH macro 2. Inserting 'break' before falling through into a case block consisting of only 'break'. We were already using this warning with GCC, but its warning behaves slightly differently. In this patch, the following differences are relevant: 1. GCC recognizes comments that say "fall through" as annotations, clang doesn't 2. GCC doesn't warn on "case N: foo(); default: break;", clang does 3. GCC doesn't warn when the case contains a switch, but falls through the outer case. I will enable the warning separately in a follow-up patch so that it can be cleanly reverted if necessary. Reviewers: alexfh, rsmith, lattner, rtrieu, EricWF, bollu Differential Revision: https://reviews.llvm.org/D53950 llvm-svn: 345882
* [mips][microMIPS] Fix the definition of MOVEP instructionSimon Atanasyan2018-09-191-113/+40
| | | | | | | | | | | | The patch fixes definition of MOVEP instruction. Two registers are used instead of register pairs. This is necessary as machine verifier cannot handle register pairs. Patch by Milena Vujosevic Janicic. Differential revision: https://reviews.llvm.org/D52035 llvm-svn: 342571
* [mips] Enable the mnemonic spell correctorSimon Atanasyan2018-09-131-1/+7
| | | | | | | | | | | | This implements suggesting alternative mnemonics when an invalid one is specified. For example `addru $9, $6, 17767` leads to the following error message: error: unknown instruction, did you mean: add, addiu, addu, maddu? Differential revision: https://reviews.llvm.org/D40646 llvm-svn: 342119
* Remove trailing spaceFangrui Song2018-07-301-3/+3
| | | | | | sed -Ei 's/[[:space:]]+$//' include/**/*.{def,h,td} lib/**/*.{cpp,h} llvm-svn: 338293
* [mips] Replace custom parsing logic for data directives by the ↵Simon Atanasyan2018-07-251-40/+3
| | | | | | | | | | | | | | | | | | | | | `addAliasForDirective` The target independent AsmParser doesn't recognise .hword, .word, .dword which are required for Mips. Currently MipsAsmParser recognises these through dispatch to MipsAsmParser::parseDataDirective. This contains equivalent logic to AsmParser::parseDirectiveValue. This patch allows reuse of AsmParser::parseDirectiveValue by making use of addAliasForDirective to support .hword, .word and .dword. Original patch provided by Alex Bradbury at D47001 was modified to fix handling of microMIPS symbols. The `AsmParser::parseDirectiveValue` calls either `EmitIntValue` or `EmitValue`. In this patch we override `EmitIntValue` in the `MipsELFStreamer` to clear a pending set of microMIPS symbols. Differential revision: https://reviews.llvm.org/D49539 llvm-svn: 337893
* [mips] Remove dead code. NFCSimon Atanasyan2018-07-111-21/+0
| | | | llvm-svn: 336777
* [mips] Addition of the [d]rem and [d]remu instructionsStefan Maksimovic2018-07-091-25/+54
| | | | | | | | | | | | | Related to http://reviews.llvm.org/D15772 Depends on http://reviews.llvm.org/D16889 Adds [D]REM[U] instructions. Patch By: Srdjan Obucina Contributions from: Simon Dardis Differential Revision: https://reviews.llvm.org/D17036 llvm-svn: 336545
* Add Triple::isMIPS()/isMIPS32()/isMIPS64(). NFCAlexander Richardson2018-06-251-5/+1
| | | | | | | | | | | | | | There are quite a few if statements that enumerate all these cases. It gets even worse in our fork of LLVM where we also have a Triple::cheri (which is mips64 + CHERI instructions) and we had to update all if statements that check for Triple::mips64 to also handle Triple::cheri. This patch helps to reduce our diff to upstream and should also make some checks more readable. Reviewed By: atanasyan Differential Revision: https://reviews.llvm.org/D48548 llvm-svn: 335493
* [mips] Mark microMIPS64 as being unsupported.Simon Dardis2018-06-191-0/+3
| | | | | | | | | | There are no provided instruction definitions for this architecture. Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D48320 llvm-svn: 335057
* [mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructionsSimon Atanasyan2018-06-011-53/+30
| | | | | | | | | | | | | | | The `MipsAsmParser::loadImmediate` can load immediates of various sizes into a register. Idea of this change is to use `loadImmediate` in the `MipsAsmParser::expandMemInst` method to load offset into a register and then call required load/store instruction. The patch removes separate `expandLoadInst` and `expandStoreInst` methods and does everything in the `expandMemInst` method to escape code duplication. Differential Revision: https://reviews.llvm.org/D47316 llvm-svn: 333774
* [mips] Process numeric register name in the .set assignment directiveSimon Atanasyan2018-05-291-8/+44
| | | | | | | | | | | | | | | | | | | | | | | | Now LLVM assembler cannot process the following code and generates an error. GNU tools support .set assignment directive with numeric register name. ``` .set r4, 4 test.s:1:11: error: invalid token in expression .set r4, $4 ^ ``` This patch teach assembler to handle such directives correctly. Unfortunately a numeric register name cannot be represented as an expression. That's why we have to maintain a separate `StringMap` in the `MipsAsmParser` to keep mapping between aliases names and register numbers. Differential revision: https://reviews.llvm.org/D47464 llvm-svn: 333428
* [mips] Cleanup the code to reduce diff with the upcoming patches. NFCSimon Atanasyan2018-05-291-10/+10
| | | | llvm-svn: 333404
* [mips] Escape else-after-return. NFCSimon Atanasyan2018-05-291-62/+63
| | | | llvm-svn: 333403
* [mips] Stop parsing a .set assignment if the first argument is not an identifierSimon Atanasyan2018-05-291-3/+2
| | | | | | | | | | | | | | Before this fix the following code triggers two error messages. The second one is at least useless: test.s:1:9: error: expected identifier after .set .set 123, $a0 ^ test-set.s:1:9: error: unexpected token, expected comma .set 123, $a0 ^ llvm-svn: 333402
* [mips] Fix the definitions of lwp, swpSimon Dardis2018-05-251-4/+21
| | | | | | | | | | | | | Rather than using a regpair operand of these instructions, use two seperate operands and a custom converter to handle the implicit second register operand. Additionally, remove the microMIPS32R6 definition as its redundant. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D47255 llvm-svn: 333288
* [mips] Remove duplicated code from the expandLoadInst. NFCSimon Atanasyan2018-05-241-36/+17
| | | | llvm-svn: 333164
* [mips] Remove redundant argument from expandLoadInst/expandStoreInst. NFCSimon Atanasyan2018-05-241-15/+13
| | | | llvm-svn: 333163
* [mips] Add precondition asserts to the expandLoadInst/expandStoreInst. NFCSimon Atanasyan2018-05-241-12/+23
| | | | llvm-svn: 333162
* [mips] Cleanup the code a bit. NFCSimon Atanasyan2018-05-241-15/+25
| | | | llvm-svn: 333161
* [mips] Add support for Global INValidate ASEPetar Jovanovic2018-05-171-0/+70
| | | | | | | | | | | | | | | | | | This includes Instructions: ginvi, ginvt, Assembler directives: .set ginv, .set noginv, .module ginv, .module noginv Attribute: ginv .MIPS.abiflags: GINV (0x20000) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D46268 llvm-svn: 332624
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-14/+14
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [mips] Add support for Virtualization ASEPetar Jovanovic2018-04-271-0/+70
| | | | | | | | | | | | | | | | | | | This includes Instructions: tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr, hypcall mfgc0, mtgc0, mfhgc0, mthgc0, dmfgc0, dmtgc0, Assembler directives: .set virt, .set novirt, .module virt, .module novirt Attribute: virt .MIPS.abiflags: VZ (0x100) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D44905 llvm-svn: 331024
* [mips] Accept 32-bit offsets for lb and lbu commandsSimon Atanasyan2018-04-261-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `lb` and `lbu` commands accepts 16-bit signed offsets. But GAS accepts larger offsets for these commands. If an offset does not fit in 16-bit range, `lb` command is translated into lui/lb or lui/addu/lb series. It's interesting that initially LLVM assembler supported this feature, but later it was broken. This patch restores support for 32-bit offsets. It replaces `mem_simm16` operand for `LB` and `LBu` definitions by the new `mem_simmptr` operand. This operand is intended to check that offset fits to the same size as using for pointers. Later we will be able to extend this rule and accepts 64-bit offsets when it is possible. Some issues remain: - The regression also affects LD, SD, LH, LHU commands. I'm going to fix them by a separate patch. - GAS accepts any 32-bit values as an offset. Now LLVM accepts signed 16-bit values and this patch extends the range to signed 32-bit offsets. In other words, the following code accepted by GAS and still triggers an error by LLVM: ``` lb $4, 0x80000004 # gas lui a0, 0x8000 lb a0, 4(a0) ``` - In case of 64-bit pointers GAS accepts a 64-bit offset and translates it to the li/dsll/lb series of commands. LLVM still rejects it. Probably this feature has never been implemented in LLVM. This issue is for a separate patch. ``` lb $4, 0x800000001 # gas li a0, 0x8000 dsll a0, a0, 0x14 lb a0, 4(a0) ``` Differential Revision: https://reviews.llvm.org/D45020 llvm-svn: 330983
* [mips] Show an error if register number is out of rangeSimon Atanasyan2018-04-241-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code does not check that a register number is in the 0-31 range. Sometimes the parser checks that later for some kinds of instructions, but that leads to unclear / incorrect error messages like that: % cat test.s .text lb $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux test.s:2:10: error: expected memory with 16-bit signed offset lb $4, 8($32) ^ Sometimes the parser just crashes: % cat test.s .text lw $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux This patch resolves the problem by checking that register number after '$' sign is in the 0-31 range. If the number is out of the range the parser shows the `invalid register number` error, but treats invalid register number as a normal one to continue parsing and catch other possible errors. Differential Revision: https://reviews.llvm.org/D45919 llvm-svn: 330732
* [mips] Add support for CRC ASEPetar Jovanovic2018-03-141-0/+77
| | | | | | | | | | | | | | | | | | | This includes Instructions: crc32b, crc32h, crc32w, crc32d, crc32cb, crc32ch, crc32cw, crc32cd Assembler directives: .set crc, .set nocrc, .module crc, .module nocrc Attribute: crc .MIPS.abiflags: CRC (0x8000) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D44176 llvm-svn: 327511
* [mips] Correct the definition of m(f|t)c(0|2)Simon Dardis2018-03-071-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | These instructions are defined as taking a GPR register and a coprocessor register for ISAs up to MIPS32. MIPS32 extended the definition to allow a selector--a value from 0 to 32--to access another register. These instructions are now internally defined as being MIPS-I instructions, but are rejected for pre-MIPS32 ISA's if they have an explicit selector which is non-zero. This deviates slightly from GAS's behaviour which rejects assembly instructions with an explicit selector for pre-MIPS32 ISAs. E.g: mfc0 $4, $5, 0 is rejected by GAS for MIPS-I to MIPS-V but will be accepted with this patch for MIPS-I to MIPS-V. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D41662 llvm-svn: 326890
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-02-221-1/+1
| | | | | | "a a" -> "a" llvm-svn: 325752
* [mips] Spectre variant two mitigation for MIPSR2Simon Dardis2018-02-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides mitigation for CVE-2017-5715, Spectre variant two, which affects the P5600 and P6600. It implements the LLVM part of -mindirect-jump=hazard. It is _not_ enabled by default for the P5600. The migitation strategy suggested by MIPS for these processors is to use hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard barrier variants of the 'jalr' and 'jr' instructions respectively. These instructions impede the execution of instruction stream until architecturally defined hazards (changes to the instruction stream, privileged registers which may affect execution) are cleared. These instructions in MIPS' designs are not speculated past. These instructions are used with the attribute +use-indirect-jump-hazard when branching indirectly and for indirect function calls. These instructions are defined by the MIPS32R2 ISA, so this mitigation method is not compatible with processors which implement an earlier revision of the MIPS ISA. Performance benchmarking of this option with -fpic and lld using -z hazardplt shows a difference of overall 10%~ time increase for the LLVM testsuite. Certain benchmarks such as methcall show a substantially larger increase in time due to their nature. Reviewers: atanasyan, zoran.jovanovic Differential Revision: https://reviews.llvm.org/D43486 llvm-svn: 325653
* [mips] Removal of microMIPS64R6Aleksandar Beserminji2017-12-111-15/+18
| | | | | | | | | | | All files and parts of files related to microMIPS4R6 are removed. When target is microMIPS4R6, errors are printed. This is LLVM part of patch. Differential Revision: https://reviews.llvm.org/D35625 llvm-svn: 320350
* [mips] Set microMIPS ASE flagAleksandar Beserminji2017-11-241-1/+3
| | | | | | | | | | This patch fixes an issue where microMIPS ASE flag is not set when a function has micromips attribute or when .set micromips directive is used. Differential Revision: https://reviews.llvm.org/D40316 llvm-svn: 318948
* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-11-141-0/+219
| | | | | | | | | | | | | | | | | | | | This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win buildbot. Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 318207
* [Asm] Add debug tracing in table-generated assembly matcherOliver Stannard2017-10-111-1/+1
| | | | | | | | | | | | | This adds debug tracing to the table-generated assembly instruction matcher, enabled by the -debug-only=asm-matcher option. The changes in the target AsmParsers are to add an MCInstrInfo reference under a consistent name, so that we can use it from table-generated code. This was already being used this way for targets that use deprecation warnings, but 5 targets did not have it, and Hexagon had it under a different name to the other backends. llvm-svn: 315445
* [mips] Partially fix PR34391Simon Dardis2017-10-101-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | Previously, the parsing of the 'subu $reg, ($reg,) imm' relied on a parser which also rendered the operand to the instruction. In some cases the general parser could construct an MCExpr which was not a MCConstantExpr which MipsAsmParser was expecting. Address this by altering the special handling to cope with unexpected inputs and fine-tune the handling of cases where an register name that is not available in the current ABI is regarded as not a match for the custom parser but also not as an outright error. Also enforces the binutils restriction that only constants are accepted. This partially resolves PR34391. Thanks to Ed Maste for reporting the issue! Reviewers: nitesh.jain, arichardson Differential Revision: https://reviews.llvm.org/D37476 llvm-svn: 315310
* [mips] implement .set dspr2 directivePetar Jovanovic2017-10-051-0/+6
| | | | | | | | | | | | Implement .set dspr2 directive with appropriate feature bits. This directive is a counterpart of -mattr=dspr2 command line option with the exception that it does not influence elf header flags. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D38537 llvm-svn: 314994
* [mips] Implement the 'dext' aliases and it's disassembly alias.Simon Dardis2017-09-141-22/+51
| | | | | | | | | | | | | | | | The other members of the dext family of instructions (dextm, dextu) are traditionally handled by the assembler selecting the right variant of 'dext' depending on the values of the position and size operands. When these instructions are disassembled, rather than reporting the actual instruction, an equivalent aliased form of 'dext' is generated and is reported. This is to mimic the behaviour of binutils. Reviewers: slthakur, nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D34887 llvm-svn: 313276
* [mips] Implement the 'dins' aliases.Simon Dardis2017-09-141-0/+36
| | | | | | | | | | | | Traditionally GAS has provided automatic selection between dins, dinsm and dinsu. Binutils also disassembles all instructions in that family as 'dins' rather than the actual instruction. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D34877 llvm-svn: 313267
* [mips] handle UImm16_AltRelaxed match typePetar Jovanovic2017-09-121-0/+1
| | | | | | | | | | | | | Currently, UImm16_AltRelaxed match type is not handled in MatchAndEmitInstruction() function, which may result in llvm_unreachable() behavior. This patch adds necessary case for this match type. Patch by Aleksandar Beserminji. Differential Revision: https://reviews.llvm.org/D37682 llvm-svn: 313077
* [mips] Follow up comments on r310460Simon Dardis2017-08-181-2/+1
| | | | | | Use dblaikie's suggestion of cast<> instead of a seperate assert. llvm-svn: 311160
* Revert "Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""Simon Dardis2017-08-141-219/+0
| | | | | | | This reverts r310834. It didn't pacify the buildbot, FileCheck is still crashing. llvm-svn: 310854
* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-08-141-0/+219
| | | | | | | | | | | | | | | | | | | | This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win buildbot. Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 310834
* [mips] PR34083 - Wimplicit-fallthrough warning in MipsAsmParser.cppSimon Dardis2017-08-091-6/+7
| | | | | | | | | | | | Assert that a binary expression is actually a binary expression, rather than potientially incorrectly attempting to handle it as a unary expression. This resolves PR34083. Thanks to Simonn Pilgrim for reporting the issue! llvm-svn: 310460
* Revert "Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""Simon Dardis2017-07-141-219/+0
| | | | | | | | | FileCheck is crashing on in the input file, so reverting again while I investigate. This reverts r308023. llvm-svn: 308030
* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""Simon Dardis2017-07-141-0/+219
| | | | | | | | | | | | | | | | | | | | | | | | Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 The last version of this patch broke one of the expensive checks buildbots, this version changes the failing test/MC/Mips/mt/invalid.s and other invalid tests to write the errors to a file and run FileCheck on that, rather than relying on the 'not llvm-mc ... <%s 2>&1 | Filecheck %s' idiom. Hopefully this will sarisfy the buildbot. llvm-svn: 308023
* Revert "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-07-131-219/+0
| | | | | | | This reverts r307836, it broke one of the buildbots. Reverting while I investigate. llvm-svn: 307939
* [mips][mt][6/7] Add support for mftr, mttr instructions.Simon Dardis2017-07-121-0/+219
| | | | | | | | | | | | | | | | | Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 307836
* [mips][mt] Correct spelling error in comment. NFCI.Simon Dardis2017-07-111-1/+1
| | | | llvm-svn: 307717
* [mips][mt][2/7] Implement .module and .set directives for the MT ASE.Simon Dardis2017-07-111-0/+59
| | | | | | | | | | | | This patch implements the .module and .set directives for the MT ASE, notably that .module sets the relevant flags in .MIPS.abiflags and .set doesn't. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35249 llvm-svn: 307716
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