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* [mips] Rename MipsAsmParser functions to conform to the LLVM Coding ↵Toma Tabacu2014-09-041-61/+61
| | | | | | | | | | | | | | Standards. No functional changes. Summary: There are still some functions which should be renamed, but they are inherited from the generic MC classes. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5068 llvm-svn: 217145
* Fix some cases where StringRef was being passed by const reference. Remove ↵Craig Topper2014-08-301-1/+1
| | | | | | const from some other StringRefs since its implicitly const already. llvm-svn: 216820
* [mips] Add assembler support for .set arch=x directive.Toma Tabacu2014-08-191-0/+38
| | | | | | | | | | | | | | | | | | Summary: This directive is similar to ".set mipsX". It is used to change the CPU target of the assembler, enabling it to accept instructions for a specific CPU. This patch only implements the r4000 CPU (which is treated internally as generic mips3) and the generic ISAs. Contains work done by Matheus Almeida. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4884 llvm-svn: 215978
* TableGen: allow use of uint64_t for available features mask.Tim Northover2014-08-181-3/+3
| | | | | | | | | | ARM in particular is getting dangerously close to exceeding 32 bits worth of possible subtarget features. When this happens, various parts of MC start to fail inexplicably as masks get truncated to "unsigned". Mostly just refactoring at present, and there's probably no way to test. llvm-svn: 215887
* [mips] Add assembler support for the "la $reg,symbol" pseudo-instruction.Toma Tabacu2014-08-141-6/+91
| | | | | | | | | | | | | | | | | | Summary: This pseudo-instruction allows the programmer to load an address from a symbolic expression into a register. Patch by David Chisnall. His work was sponsored by: DARPA, AFRL I've made some minor changes to the original, such as improving the formatting and adding some comments, and I've also added a test case. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4808 llvm-svn: 215630
* [mips] Rename [gs]etCanHaveModuleDir to more natural namesDaniel Sanders2014-08-141-4/+5
| | | | | | | | | | | | | | | | | Summary: getCanHaveModuleDir() is renamed to isModuleDirectiveAllowed(), and setCanHaveModuleDir() is renamed to forbidModuleDirective() since it is only ever given a false argument. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D4885 llvm-svn: 215628
* Re-commit: [mips] Implement .ent, .end, .frame, .mask and .fmask.Daniel Sanders2014-08-131-15/+196
| | | | | | | | | | | Patch by Matheus Almeida and Toma Tabacu The lld test failure on the previous attempt to commit was caused by the addition of the .pdr section causing the offsets it was checking to change. This has been fixed by removing the .ent/.end directives from that test since they weren't really needed. llvm-svn: 215535
* Revert r215359 - [mips] Implement .ent, .end, .frame, .mask and .fmask ↵Daniel Sanders2014-08-111-196/+15
| | | | | | | | assembler directives It seems to cause an lld test (elf/Mips/hilo16-3.test) to fail. Reverted while we investigate. llvm-svn: 215361
* [mips] Implement .ent, .end, .frame, .mask and .fmask assembler directivesDaniel Sanders2014-08-111-15/+196
| | | | | | | | Patch by Matheus Almeida and Toma Tabacu Differential Revision: http://reviews.llvm.org/D4179 llvm-svn: 215359
* [mips] Add assembler support for .set msa/nomsa directive.Daniel Sanders2014-08-071-0/+30
| | | | | | | | | | | | | | | Summary: These directives are used to toggle whether the assembler accepts MSA-specific instructions or not. Patch by Matheus Almeida and Toma Tabacu. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4783 llvm-svn: 215099
* [mips] Add assembler support for '.set mipsX'.Daniel Sanders2014-08-041-3/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch also fixes an issue with the way the Mips assembler enables/disables architecture features. Before this patch, the assembler never disabled feature bits. For example, .set mips64 .set mips32r2 would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right. Unfortunately this isn't trivial to fix because there's not an easy way to clear feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits that imply the feature being cleared and not the implied bits by the feature (there's a better explanation to the code I added). Patch by Matheus Almeida and updated by Toma Tabacu Reviewers: vmedic, matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu, llvm-commits Differential Revision: http://reviews.llvm.org/D4123 llvm-svn: 214709
* Avoid resetting the UseSoftFloat and FloatABIType on the TargetMachineEric Christopher2014-07-181-1/+1
| | | | | | | | | | Options struct and move the comment to inMips16HardFloat. Use the fact that we now know whether or not we cared about soft float to set the libcalls. Accordingly rename mipsSEUsesSoftFloat to abiUsesSoftFloat and propagate since it's no longer CPU specific. llvm-svn: 213335
* [mips] Correct .MIPS.abiflags fp_abi field for -mfpxx and without .moduleDaniel Sanders2014-07-151-1/+1
| | | | | | | | Summary: Previously all the test cases set it after initialization with '.module fp=xx'. Differential Revision: http://reviews.llvm.org/D4489 llvm-svn: 213071
* [mips] Correct the AFL_FLAGS1_ODDSPREG flag in .MIPS.abiflags when no ↵Daniel Sanders2014-07-141-3/+3
| | | | | | | | '.module oddspreg' is used Differential Revision: http://reviews.llvm.org/D4486 llvm-svn: 212932
* [mips] Add support for -modd-spreg/-mno-odd-spregDaniel Sanders2014-07-101-31/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When -mno-odd-spreg is in effect, 32-bit floating point values are not permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit floating point comparison results from being written to odd registers. This option has three purposes: * It allows support for certain MIPS implementations such as loongson-3a that do not allow the use of odd registers for single precision arithmetic. * When using -mfpxx, -mno-odd-spreg is the default and this allows us to statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1 instructions to/from odd registers are guaranteed not to appear for any reason. Once this has been established, the user can then re-enable -modd-spreg to regain the use of all 32 single-precision registers. * When using -mfp64 and -mno-odd-spreg together, an O32 extension named O32 FP64A is used as the ABI. This is intended to provide almost all functionality of an FR=1 processor but can also be executed on a FR=0 core with the assistance of a hardware compatibility mode which emulates FR=0 behaviour on an FR=1 processor. * Added '.module oddspreg' and '.module nooddspreg' each of which update the .MIPS.abiflags section appropriately * Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller doesn't have to remember to do it. * MipsABIFlags now calculates the flags1 and flags2 member on demand rather than trying to maintain them in the same format they will be emitted in. There is one portion of the -mfp64 and -mno-odd-spreg combination that is not implemented yet. Moves to/from odd-numbered double-precision registers must not use mtc1. I will fix this in a follow-up. Differential Revision: http://reviews.llvm.org/D4383 llvm-svn: 212717
* Fix r212522 - [mips] Improve encapsulation of the .MIPS.abiflags ↵Daniel Sanders2014-07-081-0/+3
| | | | | | | | implementation and limit scope of related enums Added two lines that should have been in r212522. llvm-svn: 212523
* [mips] Improve encapsulation of the .MIPS.abiflags implementation and limit ↵Daniel Sanders2014-07-081-68/+75
| | | | | | | | | | | | | | | scope of related enums Summary: Follow on to r212519 to improve the encapsulation and limit the scope of the enums. Also merged two very similar parser functions, fixed a bug where ASE's were not being reported, and marked CPR1's as being 128-bit when MSA is enabled. Differential Revision: http://reviews.llvm.org/D4384 llvm-svn: 212522
* Mips.abiflags is a new implicitly generated section that will be present on ↵Vladimir Medic2014-07-081-44/+189
| | | | | | all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it. llvm-svn: 212519
* [mips] Implementation of dli.Matheus Almeida2014-06-191-7/+90
| | | | | | | | | | | Patch by David Chisnall His work was sponsored by: DARPA, AFRL Some small modifications to the original patch: we now error if it's not possible to expand an instruction (mips-expansions-bad.s has some examples). Added some comments to the expansions. llvm-svn: 211271
* [mips] Small update to the logic behind the expansion of assembly pseudo ↵Matheus Almeida2014-06-191-9/+20
| | | | | | | | | | | | | | | | instructions. Summary: The functions that do the expansion now return false on success and true otherwise. This is so we can catch some errors during the expansion (e.g.: immediate too large). The next patch adds some test cases. Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4214 llvm-svn: 211269
* [mips] Fix expansion of memory operation if destination register is not a GPR.Matheus Almeida2014-06-181-4/+29
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The assembler tries to reuse the destination register for memory operations whenever it can but it's not possible to do so if the destination register is not a GPR. Example: ldc1 $f0, sym should expand to: lui $at, %hi(sym) ldc1 $f0, %lo(sym)($at) It's entirely wrong to expand to: lui $f0, %hi(sym) ldc1 $f0, %lo(sym)($f0) Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4173 llvm-svn: 211169
* [mips] Report correct location when "erroring" about the use of $at when ↵Matheus Almeida2014-06-181-6/+13
| | | | | | | | | | | | | | it's not available. Summary: This removes the FIXMEs from test/MC/Mips/mips-noat.s. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4172 llvm-svn: 211168
* [mips] Access $at only if necessary.Matheus Almeida2014-06-181-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch doesn't really change the logic behind expandMemInst but it allows us to assemble .S files that use .set noat with some macros. For example: .set noat lw $k0, offset($k1) Can expand to: lui $k0, %hi(offset) addu $k0, $k0, $k1 lw $k0, %lo(offset)($k0) with no need to access $at. Reviewers: dsanders, vmedic Reviewed By: dsanders, vmedic Differential Revision: http://reviews.llvm.org/D4159 llvm-svn: 211165
* [mips] Update MipsAsmParser so that it's possible to handle immediates that ↵Matheus Almeida2014-06-181-0/+2
| | | | | | | | | | | | start with the binary operator NOT (~). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4158 llvm-svn: 211163
* [mips] Remove the last usage of parseRegister from MipsAsmParser.Matheus Almeida2014-06-181-29/+33
| | | | | | | | | | | | | | Summary: Added negative test case so that we can be sure we handle erroneous situations while parsing the .cpsetup directive. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3681 llvm-svn: 211160
* [mips][mips64r6] ssnop is deprecated on MIPS32r6/MIPS64r6Daniel Sanders2014-06-161-0/+14
| | | | | | | | | | | | Summary: Depends on D4120 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: zoran.jovanovic, vmedic Differential Revision: http://reviews.llvm.org/D4121 llvm-svn: 211021
* [mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates ↵Daniel Sanders2014-06-161-0/+10
| | | | | | | | | | | | | | | | | | | | | rather than 16-bit in MIPS32r6/MIPS64r6 Summary: The error message for the invalid.s cases isn't very helpful. It happens because there is an instruction with a wider immediate that would have matched if the NotMips32r6 predicate were true. I have some WIP to improve the message but it affects most error messages for removed/re-encoded instructions on MIPS32r6/MIPS64r6 and should therefore be a separate commit. Depens on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4117 llvm-svn: 211012
* [mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-121-1/+11
| | | | | | | | | | | | | | | | | | | | Summary: Also tightened up the acceptable condition operand for these instructions on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior to that only $fcc0 is acceptable. We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's probably best to do this in InstCombine. Depends on D4111 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4112 llvm-svn: 210787
* [mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register ↵Matheus Almeida2014-06-111-0/+25
| | | | | | | | | | | | | | with Hazard Barrier). Summary: These instructions are available in ISAs >= mips32/mips64. For mips32r6/mips64r6, jr.hb has a new encoding format. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4019 llvm-svn: 210654
* AsmMatchers: Use unique_ptr to manage ownership of MCParsedAsmOperandDavid Blaikie2014-06-081-115/+101
| | | | | | | | | | | | I saw at least a memory leak or two from inspection (on probably untested error paths) and r206991, which was the original inspiration for this change. I ran this idea by Jim Grosbach a few weeks ago & he was OK with it. Since it's a basically mechanical patch that seemed sufficient - usual post-commit review, revert, etc, as needed. llvm-svn: 210427
* [mips][mips64r6] Add Relocations R_MIPS_PCHI16, R_MIPS_PCLO16 Zoran Jovanovic2014-05-271-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D3860 llvm-svn: 209659
* [mips] Implement l[wd]c3, and s[wd]c3.Daniel Sanders2014-05-081-1/+18
| | | | | | | | | | | | | | | | | | | | | Summary: These instructions were added in MIPS-I, and MIPS-II but were removed in MIPS-III. Interestingly, GAS continues to accept them when assembling for MIPS-III. For the moment, these instructions will follow GAS and accept them for MIPS-III and newer but this will be tightened up when the invalid-*.s tests are added. Depends on D3647 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3648 llvm-svn: 208311
* [mips] Move expansion of .cpsetup to target streamer.Matheus Almeida2014-05-011-51/+1
| | | | | | | | | | | | | | | Summary: There are two functional changes: 1) The directive is not expanded for the ASM->ASM code path. 2) If PIC is not set, there's no expansion for the ASM->OBJ code path (same behaviour as GAS). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3482 llvm-svn: 207741
* [mips] Add support for .cpload.Matheus Almeida2014-04-301-0/+32
| | | | | | | | | | | | | | | | | | | | Summary: This directive is used for setting up $gp in the beginning of a function. It expands to three instructions if PIC is enabled: lui $gp, %hi(_gp_disp) addui $gp, $gp, %lo(_gp_disp) addu $gp, $gp, $reg _gp_disp is a special symbol that the linker sets to the distance between the lui instruction and the context pointer (_gp). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3480 llvm-svn: 207637
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-14/+14
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-3/+3
| | | | llvm-svn: 207197
* Create MCTargetOptions.Evgeniy Stepanov2014-04-231-1/+2
| | | | | | | | | For now it contains a single flag, SanitizeAddress, which enables AddressSanitizer instrumentation of inline assembly. Patch by Yuri Gorshenin. llvm-svn: 206971
* [mips] Clang-format MipsAsmParser.Matheus Almeida2014-04-221-33/+32
| | | | | | No functional changes. llvm-svn: 206878
* [Modules] Make Support/Debug.h modular. This requires it to not changeChandler Carruth2014-04-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | behavior based on other files defining DEBUG_TYPE, which means it cannot define DEBUG_TYPE at all. This is actually better IMO as it forces folks to define relevant DEBUG_TYPEs for their files. However, it requires all files that currently use DEBUG(...) to define a DEBUG_TYPE if they don't already. I've updated all such files in LLVM and will do the same for other upstream projects. This still leaves one important change in how LLVM uses the DEBUG_TYPE macro going forward: we need to only define the macro *after* header files have been #include-ed. Previously, this wasn't possible because Debug.h required the macro to be pre-defined. This commit removes that. By defining DEBUG_TYPE after the includes two things are fixed: - Header files that need to provide a DEBUG_TYPE for some inline code can do so by defining the macro before their inline code and undef-ing it afterward so the macro does not escape. - We no longer have rampant ODR violations due to including headers with different DEBUG_TYPE definitions. This may be mostly an academic violation today, but with modules these types of violations are easy to check for and potentially very relevant. Where necessary to suppor headers with DEBUG_TYPE, I have moved the definitions below the includes in this commit. I plan to move the rest of the DEBUG_TYPE macros in LLVM in subsequent commits; this one is big enough. The comments in Debug.h, which were hilariously out of date already, have been updated to reflect the recommended practice going forward. llvm-svn: 206822
* [mips] Add initial support for NaN2008 in the back-end.Matheus Almeida2014-04-161-0/+24
| | | | | | | | | | | | This is so that EF_MIPS_NAN2008 is set if we are using IEEE 754-2008 NaN encoding (-mnan=2008). This patch also adds support for parsing '.nan legacy' and '.nan 2008' assembly directives. The handling of these directives should match GAS' behaviour i.e., the last directive in use sets the ELF header bit (EF_MIPS_NAN2008). Differential Revision: http://reviews.llvm.org/D3346 llvm-svn: 206396
* MipsAsmParser.cpp: Fix vg_leak in MipsOperand::CreateMem(). Mem.Base is ↵NAKAMURA Takumi2014-04-151-0/+16
| | | | | | managed by k_Memory itself. llvm-svn: 206293
* MipsAsmParser::ParseRegister(): Be responsible to delete an Operand on a ↵NAKAMURA Takumi2014-04-151-0/+2
| | | | | | temporary Operands. llvm-svn: 206292
* Current definition of subtract with immediate instruction aliases uses ↵Vladimir Medic2014-04-151-28/+0
| | | | | | CodeGenOnly defined instructions and post matcher expansion methods to emit real instructions add with immediate. However, they can directly alias add with immediate instruction and remove unnecessary definitions and code in MipsAsmParser.cpp. This patch makes no change in functionality, just removes unnecessary definitions and code. llvm-svn: 206272
* LLVMBuild.txt: Reformat.NAKAMURA Takumi2014-04-101-1/+1
| | | | llvm-svn: 205961
* MIPS: remove vim swap fileSaleem Abdulrasool2014-04-041-0/+0
| | | | llvm-svn: 205595
* [mips] Add initial (experimental) MIPS-IV support.Daniel Sanders2014-04-031-0/+0
| | | | | | | | | | | | | | | | | | | | | | | Summary: Adds the 'mips4' processor and a simple test of the ELF e_flags. Patch by David Chisnall His work was sponsored by: DARPA, AFRL I made one small change to the testcase so that it uses mips64-unknown-linux instead of mips4-unknown-linux. This patch indirectly adds FeatureCondMov to FeatureMips64. This is ok because it's supposed to be there anyway and it turns out that FeatureCondMov is not a predicate of any instructions at the moment (this is a bug that hasn't been noticed because there are no targets without the conditional move instructions yet). CC: theraven Differential Revision: http://llvm-reviews.chandlerc.com/D3244 llvm-svn: 205530
* [mips] Extend MipsMCExpr class to handle %higher(sym1 - sym2 + const) andSasa Stankovic2014-04-031-25/+26
| | | | | | | | | | | | | | | | | | %highest(sym1 - sym2 + const) relocations. Remove "ABS_" from VK_Mips_HI and VK_Mips_LO enums in MipsMCExpr, to be consistent with VK_Mips_HIGHER and VK_Mips_HIGHEST. This change also deletes test file test/MC/Mips/higher_highest.ll and moves its CHECK's to the new test file test/MC/Mips/higher-highest-addressing.s. The deleted file tests that R_MIPS_HIGHER and R_MIPS_HIGHEST relocations are emitted in the .o file. Since it uses -force-mips-long-branch option, it was created when MipsLongBranch's implementation was emitting R_MIPS_HIGHER and R_MIPS_HIGHEST relocations in the .o file. It was disabled when MipsLongBranch started to directly calculate offsets. Differential Revision: http://llvm-reviews.chandlerc.com/D3230 llvm-svn: 205522
* [mips] Renamed ParseAnyRegisterWithoutDollar to MatchAnyRegisterWithoutDollarDaniel Sanders2014-04-011-8/+14
| | | | | | | | | This is for consistency with other functions. The Parse* functions consume tokens and the Match* functions don't. No functional change. llvm-svn: 205305
* [mips] Extend ParseJumpTarget to support the full symbol expression syntax.Daniel Sanders2014-04-011-27/+6
| | | | | | | | | | | | | | | | Summary: This should fix the issues the D3222 caused in lld. Testcase is based on the one that failed in the buildbot. Depends on D3233 Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3234 llvm-svn: 205298
* [mips] Use AsmLexer::peekTok() to resolve the conflict between $reg and $symDaniel Sanders2014-04-011-15/+10
| | | | | | | | | | | | | | | Summary: Parsing registers no longer consume the $ token before it's confirmed whether it really has a register or not, therefore it's no longer impossible to match symbols if registers were tried first. Depends on D3232 Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3233 llvm-svn: 205297
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