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* [mips] [IAS] Rename the createShiftOr function to createLShiftOri. NFC.Toma Tabacu2015-04-281-13/+13
| | | | | | | | | | | | | | Summary: The new name is more accurate with regard to the functionality. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8968 llvm-svn: 235984
* [mips] [IAS] Store the expandLoadImm destination register in a variable. NFC.Toma Tabacu2015-04-281-11/+12
| | | | | | | | | | | | | | Summary: This removes multiple calls to getReg() and saves us column space in the source file. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8924 llvm-svn: 235978
* [mips] Correct bytes to bits in 2 comments. NFC.Toma Tabacu2015-04-271-2/+2
| | | | llvm-svn: 235891
* [mips] [IAS] Improve warning for using AT with .set noat.Toma Tabacu2015-04-271-12/+7
| | | | | | | | | | | | | | | | | Summary: Changed the warning message to show the current value of $at, similar to what clang does for typedef's, and renamed warnIfAssemblerTemporary to a more descriptive name. I also changed the type of variables which store registers from int to unsigned, updated the relevant test and tried to make the related comments clearer. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8479 llvm-svn: 235881
* [mips] [IAS] Rename getATRegNum and setATReg to {g,s}etATRegIndex. NFC.Toma Tabacu2015-04-271-8/+8
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8480 llvm-svn: 235877
* [mips] [IAS] Move NOP emission after pseudo-instruction expansion. NFC.Toma Tabacu2015-04-231-11/+9
| | | | | | As suggested in the review for http://reviews.llvm.org/D8537. llvm-svn: 235601
* [mips] [IAS] Implement the .asciiz directive.Toma Tabacu2015-04-211-0/+2
| | | | | | | | | | | | | | | | Summary: This directive is exactly the same as .asciz, except it's only used by MIPS. It is used to store null terminated strings in object files. Reviewers: rafael, dsanders, echristo Reviewed By: dsanders, echristo Subscribers: echristo, llvm-commits Differential Revision: http://reviews.llvm.org/D7530 llvm-svn: 235382
* [mips] [IAS] Add support for the .insn directive.Toma Tabacu2015-04-161-0/+21
| | | | | | | | | | | | | | | | | Summary: This assembler directive marks the current label as an instruction label in microMIPS and MIPS16. This initial implementation works only for microMIPS. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8006 llvm-svn: 235084
* [mips] [IAS] Refactor the function which checks for the availability of AT. NFC.Toma Tabacu2015-04-151-8/+13
| | | | | | | | | | | | | | | | | | Summary: Refactor MipsAsmParser::getATReg to return an internal register number instead of a register index. Also change all the int's to unsigned, seeing as the current AT register index is stored as an unsigned in MipsAssemblerOptions. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8478 llvm-svn: 234996
* [mips] [IAS] Improve comments in MipsAsmParser::expandLoadImm. NFC.Toma Tabacu2015-04-101-7/+5
| | | | llvm-svn: 234595
* [mips] [IAS] Do not generate redundant move when expanding lw/sw with symbol.Toma Tabacu2015-04-081-6/+8
| | | | | | | | | | | | | | | | | | Summary: Even though there is no 2nd register operand in the "lw/sw $8, symbol" case, we still try to find one, and we end up with $0, which makes us generate an unnecessary "addu $8, $8, $0" (a.k.a. "move $8, $8"). We can avoid this by checking if the 2nd register operand is different from $0, before generating the addu. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8055 llvm-svn: 234406
* [mips] [IAS] Allow .set assignments for already defined symbols.Toma Tabacu2015-04-071-5/+1
| | | | | | | | | | | | | | | | Summary: This is not possible when using the IAS for MIPS, but it is possible when using the IAS for other architectures and when using GAS for MIPS. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8578 llvm-svn: 234316
* Remove more superfluous .str() and replace std::string concatenation with Twine.Yaron Keren2015-03-301-1/+1
| | | | | | Following r233392, http://llvm.org/viewvc/llvm-project?rev=233392&view=rev. llvm-svn: 233555
* [mips] Move the setATReg definition inside the MipsAssemblerOptions class. NFC.Toma Tabacu2015-03-261-9/+7
| | | | | | | | | | | | | | Summary: This groups all of the MipsAssemblerOptions functionality together, making it more reader-friendly. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8445 llvm-svn: 233271
* Revert "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-03-241-41/+37
| | | | | | | | This reverts commit r233055. It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time. llvm-svn: 233068
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-03-241-37/+41
| | | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055
* Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used.Benjamin Kramer2015-03-231-0/+1
| | | | llvm-svn: 232998
* [mips] [IAS] Outline NOP creation. NFC.Toma Tabacu2015-03-161-22/+26
| | | | | | | | | | | | | | Summary: Make the code more readable by outlining NOP creation. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8320 llvm-svn: 232371
* [mips] [IAS] Add missing constraints and improve testing for the .module ↵Toma Tabacu2015-03-061-0/+18
| | | | | | | | | | | | | | | | | | directive. Summary: None of the .set directives can be used before the .module directives. The .set mips0/pop/push were not triggering this constraint. Also added testing for all the other implemented directives which are supposed to trigger this constraint. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7140 llvm-svn: 231465
* [mips] Rename the LA/LI/DLI TableGen definitions and classes. NFC.Toma Tabacu2015-03-041-8/+8
| | | | | | | | | | | | | | | | Summary: Use more reasonable names for these pseudo-instructions. As there's only one definition tied to any one of these classes, I named them with abbreviated versions of their respective class' name. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7831 llvm-svn: 231240
* Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein2015-02-191-41/+37
| | | | llvm-svn: 229841
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-02-191-37/+41
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
* [mips] Add backend support for Mips32r[35] and Mips64r[35].Daniel Sanders2015-02-181-3/+44
| | | | | | | | | | | | | | | | | Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
* [mips] [IAS] Fix using .cpsetup with local labels (PR22518).Toma Tabacu2015-02-181-5/+13
| | | | | | | | | | | | | | | | | Summary: Parse for an MCExpr instead of an Identifier and use the symbol for relocations, not just the symbol's name. This fixes errors when using local labels in .cpsetup (PR22518). Reviewers: dsanders Reviewed By: dsanders Subscribers: seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D7697 llvm-svn: 229671
* Prefer SmallVector::append/insert over push_back loops.Benjamin Kramer2015-02-171-3/+1
| | | | | | Same functionality, but hoists the vector growth out of the loop. llvm-svn: 229500
* [mips] Improve support for the .set at/noat assembler directives.Toma Tabacu2015-02-131-36/+53
| | | | | | | | | | | | | | | | | | | | | Summary: Made the following changes: Added calls to emitDirectiveSetNoAt() and emitDirectiveSetAt(). Added special emit function for .set at=$reg, emitDirectiveSetAtWithArg(unsigned RegNo). Improved parsing error checks for .set at. Refactored parser code for .set at. Improved testing of both directives. Improved code readability and comments. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7176 llvm-svn: 229097
* [mips][microMIPS] Implement movep instructionZoran Jovanovic2015-02-101-0/+78
| | | | | | Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
* [mips] Manually replace JAL pseudo-instructions with their JALR equivalent, ↵Toma Tabacu2015-01-301-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | instead of using InstAlias. Summary: This is needed by the .cprestore assembler directive. This directive needs to be able to insert an LW instruction after every JALR replacement of a JAL pseudo-instruction (and never after a JALR which has NOT been a result of a pseudo-instruction replacement). The problem with using InstAlias for these is that after it replaces the pseudo-instruction, we can't find out if the resulting JALR instruction was generated by an InstAlias or not, so we don't know whether or not to insert our LW instruction. By replacing it manually, we know when the pseudo-instruction replacement happens and we can insert the LW instruction correctly. Reviewers: dsanders Reviewed By: dsanders Subscribers: emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D5601 llvm-svn: 227568
* [mips][microMIPS] Implement SWM and LWM aliasesZoran Jovanovic2015-01-281-0/+32
| | | | | | Differential Revision: http://reviews.llvm.org/D5820 llvm-svn: 227373
* [mips][microMIPS] Implement LWGP instructionJozef Kolek2015-01-281-1/+31
| | | | | | Differential Revision: http://reviews.llvm.org/D6650 llvm-svn: 227325
* [mips] Add range checks and transformation to octeon instructions in AsmParser.Kai Nacke2015-01-271-0/+78
| | | | | | | | | | | | | | | | | This patch adds range checks to the immediate operands of octeon instructions in the AsmParser. Like gas, it applies the following transformations if the immediate is to large: bbit0 $8, 42, foo => bbit032 $8, 10, foo bbit1 $8, 46, foo => bbit132 $8, 14, foo cins $8, $31, 32, 31 => cins32 $8, $31, 0, 31 exts $7, $4, 54, 9 => exts32 $7, $4, 22, 9 Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D7080 llvm-svn: 227225
* Move the Mips target to storing the ABI in the TargetMachine ratherEric Christopher2015-01-261-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | than on MipsSubtargetInfo. This required a bit of massaging in the MC level to handle this since MC is a) largely a collection of disparate classes with no hierarchy, and b) there's no overarching equivalent to the TargetMachine, instead only the subtarget via MCSubtargetInfo (which is the base class of TargetSubtargetInfo). We're now storing the ABI in both the TargetMachine level and in the MC level because the AsmParser and the TargetStreamer both need to know what ABI we have to parse assembly and emit objects. The target streamer has a pointer to the one in the asm parser and is updated when the asm parser is created. This is fragile as the FIXME comment notes, but shouldn't be a problem in practice since we always create an asm parser before attempting to emit object code via the assembler. The TargetMachine now contains the ABI so that the DataLayout can be constructed dependent upon ABI. All testcases have been updated to use the -target-abi command line flag so that we can set the ABI without using a subtarget feature. Should be no change visible externally here. llvm-svn: 227102
* [mips] Add new error message and improve testing for parsing the .module ↵Toma Tabacu2015-01-231-26/+27
| | | | | | | | | | | | | | | | | | | | | | | directive. Summary: We used to silently ignore any empty .module's and we used to give an error saying that we found an "unexpected token at start of statement" when the value of the option wasn't an identifier (e.g. if it was a number). We now give an error saying that we "expected .module option identifier" in both of those cases. I also fixed the other tests in mips-abi-bad.s, which all seemed to be broken. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7095 llvm-svn: 226905
* Reformat.NAKAMURA Takumi2015-01-231-3/+2
| | | | llvm-svn: 226888
* MipsAsmParser.cpp: Suppress a warning introduced in r226657. [-Wunused-variable]NAKAMURA Takumi2015-01-231-3/+2
| | | | llvm-svn: 226887
* [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction BJozef Kolek2015-01-211-0/+50
| | | | | | | | | | | | | | Implement microMIPS 16-bit unconditional branch instruction B. Implemented 16-bit microMIPS unconditional instruction has real name B16, and B is an alias which expands to either B16 or BEQ according to the rules: b 256 --> b16 256 # R_MICROMIPS_PC10_S1 b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1 b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1 Differential Revision: http://reviews.llvm.org/D3514 llvm-svn: 226657
* [mips][microMIPS] Implement ADDIUPC instructionJozef Kolek2015-01-211-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D6582 llvm-svn: 226656
* Reverted revision 226577.Jozef Kolek2015-01-201-49/+0
| | | | llvm-svn: 226595
* Silencing a -Wunused-variable warning in non-asserts builds; NFC.Aaron Ballman2015-01-201-3/+2
| | | | llvm-svn: 226581
* [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction BJozef Kolek2015-01-201-0/+50
| | | | | | | | | | | | | | Implement microMIPS 16-bit unconditional branch instruction B. Implemented 16-bit microMIPS unconditional instruction has real name B16, and B is an alias which expands to either B16 or BEQ according to the rules: b 256 --> b16 256 # R_MICROMIPS_PC10_S1 b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1 b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1 Differential Revision: http://reviews.llvm.org/D3514 llvm-svn: 226577
* [cleanup] Re-sort all the #include lines in LLVM usingChandler Carruth2015-01-141-2/+2
| | | | | | | | | | | utils/sort_includes.py. I clearly haven't done this in a while, so more changed than usual. This even uncovered a missing include from the InstrProf library that I've added. No functionality changed here, just mechanical cleanup of the include order. llvm-svn: 225974
* [mips][microMIPS] Implement BEQZ16 and BNEZ16 instructionsJozef Kolek2015-01-121-0/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D5271 llvm-svn: 225627
* Replace several 'assert(false' with 'llvm_unreachable' or fold a condition ↵Craig Topper2015-01-051-3/+1
| | | | | | into the assert. llvm-svn: 225160
* Minor cleanup to all the switches after MatchInstructionImpl in all the ↵Craig Topper2015-01-031-3/+2
| | | | | | | | AsmParsers. Make sure they all have llvm_unreachable on the default path out of the switch. Remove unnecessary "default: break". Remove a 'return' after unreachable. Fix some indentation. llvm-svn: 225114
* [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructionsJozef Kolek2014-12-231-0/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D5204 llvm-svn: 224785
* [mips][microMIPS] Implement LWSP and SWSP instructionsJozef Kolek2014-12-231-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D6416 llvm-svn: 224771
* [mips][microMIPS] Implement SWP and LWP instructionsZoran Jovanovic2014-12-161-1/+47
| | | | | | Differential Revision: http://reviews.llvm.org/D5667 llvm-svn: 224338
* [mips][microMIPS] Implement SWM16 and LWM16 instructionsZoran Jovanovic2014-11-271-0/+23
| | | | | | Differential Revision: http://reviews.llvm.org/D5579 llvm-svn: 222901
* [mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructionsJozef Kolek2014-11-241-0/+46
| | | | | | Differential Revision: http://reviews.llvm.org/D5122 llvm-svn: 222653
* [mips][microMIPS] Implement 16-bit instructions registers including ZERO ↵Jozef Kolek2014-11-241-0/+12
| | | | | | | | | | instead of S0 Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17. Differential Revision: http://reviews.llvm.org/D5780 llvm-svn: 222652
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