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* [mips][micromips] Implement SWM32 and LWM32 instructionsZoran Jovanovic2014-11-191-1/+121
| | | | | | Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
* [mips] Add hardware register name "hwr_ulr" ($29)Vasileios Kalintiris2014-11-111-0/+1
| | | | | | | | | | The canonical name when printing assembly is still $29. The reason is that GAS does not accept "$hwr_ulr" at the moment. This addresses the comments from r221307, which reverted the original commit r221299. llvm-svn: 221685
* Recommit "[mips] Add names and tests for the hardware registers"Vasileios Kalintiris2014-11-111-0/+30
| | | | | | | The original commit r221299 was reverted in r221307. I removed the name "hrw_ulr" ($29) from the original commit because two tests were failing. llvm-svn: 221681
* MCAsmParserExtension has a copy of the MCAsmParser. Use it.Rafael Espindola2014-11-111-8/+49
| | | | | | Base classes were storing a second copy. llvm-svn: 221667
* [mips] Improve error/warning messages and testing for the .cpload assembler ↵Toma Tabacu2014-11-061-2/+11
| | | | | | | | | | | | | | | | | | directive. Summary: Improved warning message when using .cpload inside a reorder section and added an error message for using .cpload with Mips16 enabled. Modified the tests to fit with the changes mentioned above, added a test-case for the N32 ABI in cpload.s and did some reformatting to make the tests easier to read. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5465 llvm-svn: 221447
* [mips][microMIPS] Implement ANDI16 instructionZoran Jovanovic2014-11-051-0/+10
| | | | llvm-svn: 221367
* Reverted revisions 221351, 221352 and 221353.Zoran Jovanovic2014-11-051-10/+0
| | | | llvm-svn: 221354
* [mips][microMIPS] Implement ANDI16 instructionZoran Jovanovic2014-11-051-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D5163 llvm-svn: 221351
* Revert "[mips] Add names and tests for the hardware registers"Rafael Espindola2014-11-041-31/+0
| | | | | | | | | | | | | This reverts commit r221299. The tests LLVM :: MC/Disassembler/Mips/mips32.txt LLVM :: MC/Disassembler/Mips/mips32_le.txt were failing. llvm-svn: 221307
* [mips] Add names and tests for the hardware registersVasileios Kalintiris2014-11-041-0/+31
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5763 llvm-svn: 221299
* [mips] Improve support for the .set mips16/nomips16 assembler directives.Toma Tabacu2014-11-041-6/+22
| | | | | | | | | | | | | | | | | | | Summary: Appropriately set/clear the FeatureBit for Mips16 when these assembler directives are used and also emit ".set nomips16" (previously, only ".set mips16" was being emitted). These improvements allow for better testing of the .cpload/.cprestore assembler directives (which are not supposed to work when Mips16 is enabled). Test Plan: The test is bare-bones because there are no MC tests for Mips16 instructions (there's only one, which checks that the Mips16 ELF header flag gets set), and that suggests to me that it has not been implemented yet in the IAS. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5462 llvm-svn: 221277
* [mips][microMIPS] Implement ADDIUR1SP instructionZoran Jovanovic2014-10-231-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D5153 llvm-svn: 220477
* ps][microMIPS] Implement ADDIUR2 instructionZoran Jovanovic2014-10-231-0/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D5151 llvm-svn: 220476
* ps][microMIPS] Implement LI16 instructionZoran Jovanovic2014-10-231-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D5149 llvm-svn: 220475
* [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructionsZoran Jovanovic2014-10-231-0/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D5774 llvm-svn: 220474
* [mips][microMIPS] Implement microMIPS 16-bit instructions registersZoran Jovanovic2014-10-211-0/+19
| | | | | | Differential Revision: http://reviews.llvm.org/D5116 llvm-svn: 220273
* [mips][microMIPS] Implement ADDIUSP instructionZoran Jovanovic2014-10-101-0/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D5084 llvm-svn: 219500
* [mips][microMIPS] Implement ADDIUS5 instructionZoran Jovanovic2014-10-101-0/+19
| | | | | | Differential Revision: http://reviews.llvm.org/D5049 llvm-svn: 219495
* [mips][microMIPS] Implement JALRS16 instructionZoran Jovanovic2014-10-101-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D5027 llvm-svn: 219493
* MipsAsmParser.cpp: fix VS2012 buildHans Wennborg2014-10-031-1/+1
| | | | llvm-svn: 218991
* [mips] Print warning when using register names not available in N32/64Daniel Sanders2014-10-031-0/+30
| | | | | | | | | | | | | | | | | | | Summary: The register names t4-t7 are not available in the N32 and N64 ABIs. This patch prints a warning, when those names are used in N32/64, along with a fix-it with the correct register names. Patch by Vasileios Kalintiris Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5272 llvm-svn: 218989
* [mips] Rename emit and parse functions for the .cpload assembler directive. NFC.Toma Tabacu2014-10-011-4/+4
| | | | | | | | | | | | | | Summary: It's better if we have a consistent name for .cpload-related functions. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5437 llvm-svn: 218768
* [mips] Add assembler support for the .set nodsp directive.Toma Tabacu2014-09-171-0/+17
| | | | | | | | | | | | Summary: This directive is used to tell the assembler to reject DSP-specific instructions. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5142 llvm-svn: 217946
* [mips] Improve the error messages given by MipsAsmParser.Toma Tabacu2014-09-161-39/+42
| | | | | | | | | | | | Summary: Changed error messages to be more informative and to resemble other clang/llvm error messages (first letter is lower case, no ending punctuation) and updated corresponding tests. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5065 llvm-svn: 217873
* [mips] Use early exit in MipsAsmParser::matchCPURegisterName(). NFC.Toma Tabacu2014-09-151-17/+18
| | | | | | | | Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5270 llvm-svn: 217774
* [mips][microMIPS] Implement BGEZALS and BLTZALS instructionsZoran Jovanovic2014-09-121-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D5004 llvm-svn: 217678
* [mips][microMIPS] Implement JALS and JALRS instructions.Zoran Jovanovic2014-09-121-4/+20
| | | | | | Differential Revision: http://reviews.llvm.org/D5003 llvm-svn: 217676
* Remove a temporary variable and just construct a unique_ptr directly using ↵Craig Topper2014-09-121-9/+6
| | | | | | make_unique. llvm-svn: 217655
* [mips] Add assembler support for .set mips0 directive.Toma Tabacu2014-09-091-0/+16
| | | | | | | | | | | | | | | | | | Summary: This directive is used to reset the assembler options to their initial values. Assembly programmers use it in conjunction with the ".set mipsX" directives. This patch depends on the .set push/pop directive (http://reviews.llvm.org/D4821). Contains work done by Matheus Almeida. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4957 llvm-svn: 217438
* [mips] Add assembler support for .set push/pop directive.Toma Tabacu2014-09-091-17/+84
| | | | | | | | | | | | | | | Summary: These directives are used to save the current assembler options (in the case of ".set push") and restore the previously saved options (in the case of ".set pop"). Contains work done by Matheus Almeida. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4821 llvm-svn: 217432
* [mips] Change Feature-related types from unsigned to uint64_t in ↵Toma Tabacu2014-09-051-2/+2
| | | | | | | | | | | | | | MipsAsmParser. No functional changes. Summary: Found a couple of cases where unsigned was still being used. These two should be the last ones in the (entire) Mips backend. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5028 llvm-svn: 217257
* [mips] Rename data members and member functions in MipsAssemblerOptions.Toma Tabacu2014-09-051-14/+14
| | | | | | | | | | | | Summary: Use the naming convention from the LLVM Coding Standards. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4972 llvm-svn: 217254
* [mips] Rename MipsAsmParser functions to conform to the LLVM Coding ↵Toma Tabacu2014-09-041-61/+61
| | | | | | | | | | | | | | Standards. No functional changes. Summary: There are still some functions which should be renamed, but they are inherited from the generic MC classes. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5068 llvm-svn: 217145
* Fix some cases where StringRef was being passed by const reference. Remove ↵Craig Topper2014-08-301-1/+1
| | | | | | const from some other StringRefs since its implicitly const already. llvm-svn: 216820
* [mips] Add assembler support for .set arch=x directive.Toma Tabacu2014-08-191-0/+38
| | | | | | | | | | | | | | | | | | Summary: This directive is similar to ".set mipsX". It is used to change the CPU target of the assembler, enabling it to accept instructions for a specific CPU. This patch only implements the r4000 CPU (which is treated internally as generic mips3) and the generic ISAs. Contains work done by Matheus Almeida. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4884 llvm-svn: 215978
* TableGen: allow use of uint64_t for available features mask.Tim Northover2014-08-181-3/+3
| | | | | | | | | | ARM in particular is getting dangerously close to exceeding 32 bits worth of possible subtarget features. When this happens, various parts of MC start to fail inexplicably as masks get truncated to "unsigned". Mostly just refactoring at present, and there's probably no way to test. llvm-svn: 215887
* [mips] Add assembler support for the "la $reg,symbol" pseudo-instruction.Toma Tabacu2014-08-141-6/+91
| | | | | | | | | | | | | | | | | | Summary: This pseudo-instruction allows the programmer to load an address from a symbolic expression into a register. Patch by David Chisnall. His work was sponsored by: DARPA, AFRL I've made some minor changes to the original, such as improving the formatting and adding some comments, and I've also added a test case. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4808 llvm-svn: 215630
* [mips] Rename [gs]etCanHaveModuleDir to more natural namesDaniel Sanders2014-08-141-4/+5
| | | | | | | | | | | | | | | | | Summary: getCanHaveModuleDir() is renamed to isModuleDirectiveAllowed(), and setCanHaveModuleDir() is renamed to forbidModuleDirective() since it is only ever given a false argument. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D4885 llvm-svn: 215628
* Re-commit: [mips] Implement .ent, .end, .frame, .mask and .fmask.Daniel Sanders2014-08-131-15/+196
| | | | | | | | | | | Patch by Matheus Almeida and Toma Tabacu The lld test failure on the previous attempt to commit was caused by the addition of the .pdr section causing the offsets it was checking to change. This has been fixed by removing the .ent/.end directives from that test since they weren't really needed. llvm-svn: 215535
* Revert r215359 - [mips] Implement .ent, .end, .frame, .mask and .fmask ↵Daniel Sanders2014-08-111-196/+15
| | | | | | | | assembler directives It seems to cause an lld test (elf/Mips/hilo16-3.test) to fail. Reverted while we investigate. llvm-svn: 215361
* [mips] Implement .ent, .end, .frame, .mask and .fmask assembler directivesDaniel Sanders2014-08-111-15/+196
| | | | | | | | Patch by Matheus Almeida and Toma Tabacu Differential Revision: http://reviews.llvm.org/D4179 llvm-svn: 215359
* [mips] Add assembler support for .set msa/nomsa directive.Daniel Sanders2014-08-071-0/+30
| | | | | | | | | | | | | | | Summary: These directives are used to toggle whether the assembler accepts MSA-specific instructions or not. Patch by Matheus Almeida and Toma Tabacu. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4783 llvm-svn: 215099
* [mips] Add assembler support for '.set mipsX'.Daniel Sanders2014-08-041-3/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch also fixes an issue with the way the Mips assembler enables/disables architecture features. Before this patch, the assembler never disabled feature bits. For example, .set mips64 .set mips32r2 would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right. Unfortunately this isn't trivial to fix because there's not an easy way to clear feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits that imply the feature being cleared and not the implied bits by the feature (there's a better explanation to the code I added). Patch by Matheus Almeida and updated by Toma Tabacu Reviewers: vmedic, matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu, llvm-commits Differential Revision: http://reviews.llvm.org/D4123 llvm-svn: 214709
* Avoid resetting the UseSoftFloat and FloatABIType on the TargetMachineEric Christopher2014-07-181-1/+1
| | | | | | | | | | Options struct and move the comment to inMips16HardFloat. Use the fact that we now know whether or not we cared about soft float to set the libcalls. Accordingly rename mipsSEUsesSoftFloat to abiUsesSoftFloat and propagate since it's no longer CPU specific. llvm-svn: 213335
* [mips] Correct .MIPS.abiflags fp_abi field for -mfpxx and without .moduleDaniel Sanders2014-07-151-1/+1
| | | | | | | | Summary: Previously all the test cases set it after initialization with '.module fp=xx'. Differential Revision: http://reviews.llvm.org/D4489 llvm-svn: 213071
* [mips] Correct the AFL_FLAGS1_ODDSPREG flag in .MIPS.abiflags when no ↵Daniel Sanders2014-07-141-3/+3
| | | | | | | | '.module oddspreg' is used Differential Revision: http://reviews.llvm.org/D4486 llvm-svn: 212932
* [mips] Add support for -modd-spreg/-mno-odd-spregDaniel Sanders2014-07-101-31/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When -mno-odd-spreg is in effect, 32-bit floating point values are not permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit floating point comparison results from being written to odd registers. This option has three purposes: * It allows support for certain MIPS implementations such as loongson-3a that do not allow the use of odd registers for single precision arithmetic. * When using -mfpxx, -mno-odd-spreg is the default and this allows us to statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1 instructions to/from odd registers are guaranteed not to appear for any reason. Once this has been established, the user can then re-enable -modd-spreg to regain the use of all 32 single-precision registers. * When using -mfp64 and -mno-odd-spreg together, an O32 extension named O32 FP64A is used as the ABI. This is intended to provide almost all functionality of an FR=1 processor but can also be executed on a FR=0 core with the assistance of a hardware compatibility mode which emulates FR=0 behaviour on an FR=1 processor. * Added '.module oddspreg' and '.module nooddspreg' each of which update the .MIPS.abiflags section appropriately * Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller doesn't have to remember to do it. * MipsABIFlags now calculates the flags1 and flags2 member on demand rather than trying to maintain them in the same format they will be emitted in. There is one portion of the -mfp64 and -mno-odd-spreg combination that is not implemented yet. Moves to/from odd-numbered double-precision registers must not use mtc1. I will fix this in a follow-up. Differential Revision: http://reviews.llvm.org/D4383 llvm-svn: 212717
* Fix r212522 - [mips] Improve encapsulation of the .MIPS.abiflags ↵Daniel Sanders2014-07-081-0/+3
| | | | | | | | implementation and limit scope of related enums Added two lines that should have been in r212522. llvm-svn: 212523
* [mips] Improve encapsulation of the .MIPS.abiflags implementation and limit ↵Daniel Sanders2014-07-081-68/+75
| | | | | | | | | | | | | | | scope of related enums Summary: Follow on to r212519 to improve the encapsulation and limit the scope of the enums. Also merged two very similar parser functions, fixed a bug where ASE's were not being reported, and marked CPR1's as being 128-bit when MSA is enabled. Differential Revision: http://reviews.llvm.org/D4384 llvm-svn: 212522
* Mips.abiflags is a new implicitly generated section that will be present on ↵Vladimir Medic2014-07-081-44/+189
| | | | | | all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it. llvm-svn: 212519
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