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* Add a MCTargetStreamer interface.Rafael Espindola2013-10-081-2/+8
| | | | | | | | | | | | | This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. llvm-svn: 192181
* Remove some really nasty uses of hasRawTextSupport.Rafael Espindola2013-10-051-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When MC was first added, targets could use hasRawTextSupport to keep features working before they were added to the MC interface. The design goal of MC is to provide an uniform api for printing assembly and object files. Short of relaxations and other corner cases, a object file is just another representation of the assembly. It was never the intention that targets would keep doing things like if (hasRawTextSupport()) Set flags in one way. else Set flags in another way. When they do that they create two code paths and the object file is no longer just another representation of the assembly. This also then requires testing with llc -filetype=obj, which is extremelly brittle. This patch removes some of these hacks by replacing them with smaller ones. The ARM flag setting is trivial, so I just moved it to the constructor. For Mips, the patch adds two temporary hack directives that allow the assembly to represent the same things as the object file was already able to. The hope is that the mips developers will replace the hack directives with the same ones that gas uses and drop the -print-hack-directives flag. I will also try to implement a target streamer interface, so that we can move this out of the common code. In summary, for any new work, two rules of the thumb are * Don't use "llc -filetype=obj" in tests. * Don't add calls to hasRawTextSupport. llvm-svn: 192035
* reverting per requestJack Carter2013-10-041-19/+0
| | | | llvm-svn: 191992
* [MC][AsmParser] Hook for post assembly file processingJack Carter2013-10-041-0/+19
| | | | | | | | | | | | | | | | | | | | | This patch handles LLVM standalone assembler (llvm-mc) ELF flag setting based on input file directive processing. Mips assembly requires processing inline directives that directly and indirectly affect the output ELF header flags. This patch handles one ".abicalls". To process these directives we are following the model the code generator uses by storing state in a container as we go through processing and when we detect the end of input file processing, AsmParser is notified and we update the ELF header flags through a MipsELFStreamer method with a call from MCTargetAsmParser::emitEndOfAsmFile(MCStreamer &OutStreamer). This patch will allow other targets the same functionality. Jack llvm-svn: 191982
* This patch adds aliases for Mips sub instruction with immediate operands. ↵Vladimir Medic2013-10-011-0/+22
| | | | | | Corresponding test cases are added. llvm-svn: 191734
* [mips][msa] Direct Object Emission support for the MSA instruction set. Jack Carter2013-09-251-4/+129
| | | | | | | | | | In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida llvm-svn: 191412
* This patch implements Mips load/store instructions from/to coprocessor 2. ↵Vladimir Medic2013-09-161-1/+35
| | | | | | Test cases are added. llvm-svn: 190780
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-121-2/+8
| | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. llvm-svn: 190598
* Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of ↵Vladimir Medic2013-09-101-0/+4
| | | | | | register when PFU is 32 bit. llvm-svn: 190397
* Remove obsolete code from MipsAsmParser.cpp.Vladimir Medic2013-09-101-22/+0
| | | | llvm-svn: 190396
* [mips] Use ptr_rc to simplify definitions of base+index load/store instructions.Akira Hatanaka2013-08-281-1/+92
| | | | | | Also, fix predicates. llvm-svn: 189432
* [mips] Define register class FGRH32 for the high half of the 64-bit floatingAkira Hatanaka2013-08-201-0/+15
| | | | | | | | point registers. We will need this register class later when we add definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead. llvm-svn: 188842
* [mips] Fix bug in parsing accumulator registers.Akira Hatanaka2013-08-141-2/+2
| | | | llvm-svn: 188344
* [mips] Use register operands instead of register classes in DSP instructionAkira Hatanaka2013-08-141-1/+83
| | | | | | definitions. llvm-svn: 188343
* This patch introduces changes to MipsAsmParser register parsing routines. ↵Vladimir Medic2013-08-131-176/+146
| | | | | | The code now follows more deterministic path and makes the code more efficient and easier to maintain. llvm-svn: 188264
* [mips] Rename accumulator register classes and FP register operands.Akira Hatanaka2013-08-081-7/+7
| | | | llvm-svn: 188020
* [mips] Delete register class HWRegs64.Akira Hatanaka2013-08-081-39/+0
| | | | | | No functionality change. llvm-svn: 188016
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-061-23/+23
| | | | llvm-svn: 187832
* [mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates ofAkira Hatanaka2013-08-061-3/+0
| | | | | | instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
* [mips] Replace usages of register classes with register operands. Also, removeAkira Hatanaka2013-08-061-2/+44
| | | | | | | unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print jalr InstAliases in MipsInstPrinter::printAlias. llvm-svn: 187821
* This patch implements parsing of mips FCC register operands. The example ↵Vladimir Medic2013-07-301-1/+42
| | | | | | instructions have been added to test files. llvm-svn: 187410
* [mips] Make MipsAsmParser::parseCCRRegs return NoMatch instead of ParseFailAkira Hatanaka2013-07-241-2/+2
| | | | | | | when there wasn't a match. This behavior is consistent with other register parsing methods. llvm-svn: 187063
* Split generated asm mnemonic matching table into a separate table for each ↵Craig Topper2013-07-241-1/+1
| | | | | | | | asm variant. This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o. llvm-svn: 187026
* [mips] Fix MipsAsmParser::parseCCRRegs.Akira Hatanaka2013-07-221-17/+10
| | | | | | | | Enable parsing all 32 floating point control registers $0-31 and stop trying to parse floating point condition code register $fcc0. Also, return ParseFail if the operand being parsed is not in the expected format. llvm-svn: 186861
* This patch extends mips register parsing methods to allow indexed register ↵Vladimir Medic2013-07-181-0/+12
| | | | | | parsing. The corresponding test cases are added to the patch. llvm-svn: 186567
* This patch checks for valid mnemonics at the beginning of parseInstruction ↵Vladimir Medic2013-07-171-0/+5
| | | | | | method, thus giving the user the right error message for non-existing instructions. llvm-svn: 186512
* This patch represents Mips utilization of r186388 code that alows asm ↵Vladimir Medic2013-07-161-127/+10
| | | | | | matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient. llvm-svn: 186397
* This patch introduces RegisterOperand class into Mips FPU instruction ↵Vladimir Medic2013-06-241-54/+83
| | | | | | definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser. llvm-svn: 184716
* Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU ↵Vladimir Medic2013-06-201-48/+58
| | | | | | registers. llvm-svn: 184411
* The RenderMethod field in RegisterOperand class sets the name of the method ↵Vladimir Medic2013-06-191-14/+1
| | | | | | on the target specific operand to call to add the target specific operand to an MCInst. This patch defines RenderMethod for mips RegisterOperand classes and removes redundant code from MipsAsmParser.cpp llvm-svn: 184292
* Use pointers to the MCAsmInfo and MCRegInfo.Bill Wendling2013-06-181-1/+1
| | | | | | | | | Someone may want to do something crazy, like replace these objects if they change or something. No functionality change intended. llvm-svn: 184175
* Test commit for user vmedic, to verify commit access. One line of comment is ↵Vladimir Medic2013-06-041-1/+1
| | | | | | added to MipsAsmParser.cpp. llvm-svn: 183215
* Mips assembler: Improve set register alias handlingJack Carter2013-05-281-5/+28
| | | | | | | | | | | | | | | | This patch solves the problem of numeric register values not being accepted: ../set_alias.s:1:11: error: expected valid expression after comma .set r4,$4 ^ The parsing of .set directive is changed and handling of symbols in code as well to enable this feature. The test example is added. Patch by Vladimir Medic llvm-svn: 182807
* Mips assembler: .set reorder supportJack Carter2013-04-251-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | Mips have delayslots for certain instructions like jumps and branches. These are instructions that follow the branch or jump and are executed before the jump or branch is completed. Early Mips compilers could not cope with delayslots and left them up to the assembler. The assembler would fill the delayslots with the appropriate instruction, usually just a nop to allow correct runtime behavior. The default behavior for this is set with .set reorder. To tell the assembler that you don't want it to mess with the delayslot one used .set noreorder. For backwards compatibility we need to support .set reorder and have it be the default behavior in the assembler. Our support for it is to insert a NOP directly after an instruction with a delayslot when in .set reorder mode. Contributer: Vladimir Medic llvm-svn: 180584
* Mips assembler: formatting and comment changes.Jack Carter2013-04-181-302/+294
| | | | | | This patch should not have any functional changes. llvm-svn: 179737
* Fix -Werror build.Evgeniy Stepanov2013-04-171-0/+2
| | | | | | Broken in r179657. llvm-svn: 179669
* Mips assembler: Enable handling of nested expressionsJack Carter2013-04-171-108/+200
| | | | | | | | | | This patch allows the Mips assembler to parse and emit nested expressions as instruction operands. It also extends the expansion of memory instructions when an offset is given as an expression. Contributer: Vladimir Medic llvm-svn: 179657
* Mips assembler: Explicit floating point condition register recognition.Jack Carter2013-04-151-0/+3
| | | | | | | | | | This patch allows the assembler to recognize $fcc0 as a valid register for conditional move instructions. Corresponding test cases have been added. Contributer: Vladimir Medic llvm-svn: 179567
* This patch that enables the Mips assembler to use symbols for offset for ↵Jack Carter2013-03-221-17/+150
| | | | | | | | | | | | instructions This patch uses the generated instruction info tables to identify memory/load store instructions. After successful matching and based on the operand type and size, it generates additional instructions to the output. Contributor: Vladimir Medic llvm-svn: 177685
* This patch enables the Mips .set directive to define aliasesJack Carter2013-03-211-6/+93
| | | | | | | | | | | | | | | | The .set directive in the Mips the assembler can be used to set the value of a symbol to an expression. This changes the symbol's value and type to conform to the expression's. Syntax: .set symbol, expression This patch implements the parsing of the above syntax and enables the parser to use defined symbols when parsing operands. Contributor: Vladimir Medic llvm-svn: 177667
* Silence anonymous type in anonymous union warnings.Eric Christopher2013-03-151-18/+23
| | | | llvm-svn: 177135
* Mips specific standalone assembler addressing mode %hi and %lo.Jack Carter2013-02-211-0/+5
| | | | | | | | | | | | The constructs %hi() and %lo() represent the high and low 16 bits of the address. Because the 16 bit offset field of an LW instruction is interpreted as signed, if bit 15 of the low part is 1 then the low part will act as a negative and 1 needs to be added to the high part. Contributer: Vladimir Medic llvm-svn: 175707
* ELF symbol table field st_other support, Jack Carter2013-02-201-85/+84
| | | | | | | | | | | | | | | | | | | | excluding visibility bits. Mips specific standalone assembler directive "set at". This directive changes the general purpose register that the assembler will use when given the symbolic register name $at. This does not include negative testing. That will come in a future patch. A side affect of this patch recognizes the different GPR register names for temporaries between old abi and new abi so a test case for that is included. Contributer: Vladimir Medic llvm-svn: 175686
* MCParser: Update method names per coding guidelines.Jim Grosbach2013-02-201-19/+19
| | | | | | | | | | | | | | | | | | | s/AddDirectiveHandler/addDirectiveHandler/ s/ParseMSInlineAsm/parseMSInlineAsm/ s/ParseIdentifier/parseIdentifier/ s/ParseStringToEndOfStatement/parseStringToEndOfStatement/ s/ParseEscapedString/parseEscapedString/ s/EatToEndOfStatement/eatToEndOfStatement/ s/ParseExpression/parseExpression/ s/ParseParenExpression/parseParenExpression/ s/ParseAbsoluteExpression/parseAbsoluteExpression/ s/CheckForValidSection/checkForValidSection/ http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly No functional change intended. llvm-svn: 175675
* This patch implements parsing the .wordJack Carter2013-01-251-7/+42
| | | | | | | | directive for the Mips assembler. Contributer: Vladimir Medic llvm-svn: 173407
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-171-1/+7
| | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic llvm-svn: 172685
* reverting 172579Jack Carter2013-01-161-4/+1
| | | | llvm-svn: 172594
* Akira,Jack Carter2013-01-161-1/+4
| | | | | | | | | | | | Hope you are feeling better. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic llvm-svn: 172579
* MipsAsmParser: Try to unbreak tests to add extra check.NAKAMURA Takumi2013-01-121-2/+2
| | | | llvm-svn: 172315
* This patch tackles the problem of parsing Mips Jack Carter2013-01-121-77/+253
| | | | | | | | | | | | | | | | | | register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
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