| Commit message (Collapse) | Author | Age | Files | Lines |
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in patches. :-(
llvm-svn: 115396
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llvm-svn: 115395
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llvm[2]: Updated LibDeps.txt because dependencies changed
llvm[2]: Checking for cyclic dependencies between LLVM libraries.
find-cycles.pl: Circular dependency between *.a files:
find-cycles.pl: libLLVMMSP430AsmPrinter.a libLLVMMSP430CodeGen.a
llvm-svn: 115393
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is more familiar with CMake please review?
llvm-svn: 115391
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'InstPrinter' to fall into line with the other MC-ized assembly printer
using targets.
llvm-svn: 115367
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InstPrinter) subdir
llvm-svn: 115363
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use MC instructions in the printInstruction() method via the tablegen flag
for it rather than a #define prior to including the autogenerated bits.
llvm-svn: 115238
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llvm-svn: 114999
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passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
llvm-svn: 114471
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llvm-svn: 114461
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llvm-svn: 114410
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llvm-svn: 114391
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build systems...
This problem is unrelated to the recent dependency tracking change. It
seems like noone noticed the problem because I don't think anyone compiles
any target other than X86 on windows.
llvm-svn: 113727
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llvm-svn: 113073
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to try to re-use scavenged frame index reference registers. rdar://8277890
llvm-svn: 112241
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llvm-svn: 111835
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llvm-svn: 110460
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llvm-svn: 110410
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address of the static
ID member as the sole unique type identifier. Clean up APIs related to this change.
llvm-svn: 110396
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llvm-svn: 109224
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ARM/PPC/MSP430-specific code (which are the only targets that
implement the hook) can directly reference their target-specific
instrinfo classes.
llvm-svn: 109171
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llvm-svn: 108812
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llvm-svn: 108567
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thus is a much more meaningful name.
llvm-svn: 108563
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llvm-svn: 108366
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assert()s, switching to void-casts. Removed an unneeded Compiler.h include as
a result. There are two other uses in LLVM, but they're not due to assert()s,
so I've left them alone.
llvm-svn: 108088
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llvm-svn: 108080
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code can do calling-convention queries. This obviates OutputArgReg.
llvm-svn: 107786
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llvm-svn: 107710
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the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
llvm-svn: 107691
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llvm-svn: 107668
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the pseudo instruction is not at the end of the block.
llvm-svn: 107655
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slots so it's always false.
llvm-svn: 107550
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Patch by Ben Ransford!
llvm-svn: 106722
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llvm-svn: 106455
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llvm-svn: 106448
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addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
llvm-svn: 106243
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llvm-svn: 105322
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A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
llvm-svn: 104704
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This reverts commit 104654.
llvm-svn: 104660
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A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
llvm-svn: 104654
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SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.
llvm-svn: 104627
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llvm-svn: 104571
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structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
llvm-svn: 104563
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llvm-svn: 104513
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llvm-svn: 104421
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TargetMachine.h and put it in its own namespace.
llvm-svn: 104147
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to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.
llvm-svn: 103495
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Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.
llvm-svn: 103481
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doesn't have to guess.
llvm-svn: 103194
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