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* Explicitly declare a library dependency of LLVM*Desc toOscar Fuentes2011-07-281-0/+2
| | | | | | | | | | | | | | | | | | | LLVM*AsmPrinter. GenLibDeps.pl fails to detect vtable references. As this is the only referenced symbol from LLVM*Desc to LLVM*AsmPrinter on optimized builds, the algorithm that creates the list of libraries to be linked into tools doesn't know about the dependency and sometimes places the libraries on the wrong order, yielding error messages like this: ../../lib/libLLVMARMDesc.a(ARMMCTargetDesc.cpp.o): In function `llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)': ARMMCTargetDesc.cpp:(.text._ZN4llvm14ARMInstPrinterC1ERKNS_9MCAsmInfoE [llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)]+0x2a): undefined reference to `vtable for llvm::ARMInstPrinter' llvm-svn: 136328
* Clean up a pile of hacks in our CMake build relating to TableGen.Chandler Carruth2011-07-263-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first problem to fix is to stop creating synthetic *Table_gen targets next to all of the LLVM libraries. These had no real effect as CMake specifies that add_custom_command(OUTPUT ...) directives (what the 'tablegen(...)' stuff expands to) are implicitly added as dependencies to all the rules in that CMakeLists.txt. These synthetic rules started to cause problems as we started more and more heavily using tablegen files from *subdirectories* of the one where they were generated. Within those directories, the set of tablegen outputs was still available and so these synthetic rules added them as dependencies of those subdirectories. However, they were no longer properly associated with the custom command to generate them. Most of the time this "just worked" because something would get to the parent directory first, and run tablegen there. Once run, the files existed and the build proceeded happily. However, as more and more subdirectories have started using this, the probability of this failing to happen has increased. Recently with the MC refactorings, it became quite common for me when touching a large enough number of targets. To add insult to injury, several of the backends *tried* to fix this by adding explicit dependencies back to the parent directory's tablegen rules, but those dependencies didn't work as expected -- they weren't forming a linear chain, they were adding another thread in the race. This patch removes these synthetic rules completely, and adds a much simpler function to declare explicitly that a collection of tablegen'ed files are referenced by other libraries. From that, we can add explicit dependencies from the smaller libraries (such as every architectures Desc library) on this and correctly form a linear sequence. All of the backends are updated to use it, sometimes replacing the existing attempt at adding a dependency, sometimes adding a previously missing dependency edge. Please let me know if this causes any problems, but it fixes a rather persistent and problematic source of build flakiness on our end. llvm-svn: 136023
* Separate MCInstPrinter registration from AsmPrinter registration.Evan Cheng2011-07-252-10/+13
| | | | llvm-svn: 135974
* createXXXMCCodeGenInfo should be static.Evan Cheng2011-07-231-2/+2
| | | | llvm-svn: 135826
* Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,Evan Cheng2011-07-221-20/+16
| | | | | | InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC. llvm-svn: 135812
* - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.Evan Cheng2011-07-203-5/+8
| | | | | | | | - Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. llvm-svn: 135580
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-193-6/+17
| | | | | | | (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. llvm-svn: 135468
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-183-21/+12
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner2011-07-182-5/+5
| | | | llvm-svn: 135375
* Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatestEvan Cheng2011-07-151-0/+2
| | | | | | | solution but it is a small step towards removing the horror that is TargetAsmInfo. llvm-svn: 135237
* Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng2011-07-147-8/+13
| | | | | | MCTargetDesc to prepare for next round of changes. llvm-svn: 135219
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-1410-38/+111
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-112-1/+12
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Change createAsmParser to take a MCSubtargetInfo instead of triple,Evan Cheng2011-07-091-0/+13
| | | | | | | | | CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. llvm-svn: 134795
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-082-2/+3
| | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-072-5/+7
| | | | llvm-svn: 134606
* createMCInstPrinter doesn't need TargetMachine anymore.Evan Cheng2011-07-062-4/+2
| | | | llvm-svn: 134525
* Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng2011-07-014-4/+4
| | | | llvm-svn: 134281
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-012-3/+3
| | | | llvm-svn: 134259
* - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-012-1/+8
| | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. llvm-svn: 134257
* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-012-3/+6
| | | | llvm-svn: 134244
* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-304-6/+9
| | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! llvm-svn: 134127
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-282-6/+6
| | | | llvm-svn: 134030
* Hide more details in tablegen generated MCRegisterInfo ctor function.Evan Cheng2011-06-281-2/+1
| | | | llvm-svn: 134027
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-284-6/+8
| | | | llvm-svn: 134024
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-5/+5
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-275-9/+9
| | | | | | into XXXGenRegisterInfo.inc. llvm-svn: 133922
* Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng2011-06-243-6/+9
| | | | | | | | | | | | target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. llvm-svn: 133782
* Use set operations instead of plain lists to enumerate register classes.Jakob Stoklund Olesen2011-06-151-4/+4
| | | | | | | | | | | | This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. llvm-svn: 133105
* Remove custom allocation order boilerplate that is no longer needed.Jakob Stoklund Olesen2011-06-092-36/+6
| | | | | | | | | | | | | | | | | | | | The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. llvm-svn: 132781
* Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher2011-06-081-8/+8
| | | | | | | | No functional change. Part of PR6965 llvm-svn: 132763
* Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola2011-05-302-0/+6
| | | | | | | | directives. Fixes PR9826. llvm-svn: 132317
* Make the logic for determining function alignment more explicit. No ↵Eli Friedman2011-05-062-8/+3
| | | | | | functionality change. llvm-svn: 131012
* Implement MSP430RegisterInfo::getMatchingSuperRegClass to enable cross-classJakob Stoklund Olesen2011-05-041-0/+7
| | | | | | coalescing. llvm-svn: 130814
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* We need to pass the TargetMachine object to the InstPrinter if we are printingBill Wendling2011-03-212-3/+5
| | | | | | | | | the alias of an InstAlias instead of the thing being aliased. Because we need to know the features that are valid for an InstAlias. This is part of a work-in-progress. llvm-svn: 127986
* Allow targets to specify a the type of the RHS of a shift parameterized on ↵Owen Anderson2011-02-252-5/+3
| | | | | | the type of the LHS. llvm-svn: 126518
* Use explicit add_subdirectory's for LLVM target sublibraries insteadOscar Fuentes2011-02-201-0/+3
| | | | | | | | | of testing for its presence at cmake time. This way the build automatically regenerates the makefiles when a svn update brings in a new sublibrary. llvm-svn: 126068
* Teach frame lowering to ignore debug values after the terminators.Jakob Stoklund Olesen2011-01-131-1/+1
| | | | llvm-svn: 123399
* Update CMake stuffAnton Korobeynikov2011-01-101-1/+1
| | | | llvm-svn: 123171
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-106-30/+32
| | | | | | and fixes here and there. llvm-svn: 123170
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-231-8/+8
| | | | llvm-svn: 122513
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-4/+4
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* Move callee-saved regs spills / reloads to TFIAnton Korobeynikov2010-11-274-51/+56
| | | | llvm-svn: 120228
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-185-33/+37
| | | | llvm-svn: 119740
* Attempt to unbreak cmake-based buildsAnton Korobeynikov2010-11-151-0/+1
| | | | llvm-svn: 119098
* First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ↵Anton Korobeynikov2010-11-156-146/+218
| | | | | | out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place llvm-svn: 119097
* Inside the calling convention logic LocVT is always a simpleDuncan Sands2010-11-031-1/+1
| | | | | | | | | | value type, so there is no point in passing it around using an EVT. Use the simpler MVT everywhere. Rather than trying to propagate this information maximally in all the code that using the calling convention stuff, I chose to do a mainly low impact change instead. llvm-svn: 118167
* Re-apply r115363 and r115366 now that r115525 has removed the un-needed headerJim Grosbach2010-10-059-4/+4
| | | | | | | | | that caused the circular dependencies on Linux. Built OK for me on OSX and Linux (Ubuntu) with configure/make and CMake. Will keep an eye on the bots.... llvm-svn: 115582
* Remove unneeded headerJim Grosbach2010-10-041-1/+0
| | | | llvm-svn: 115525
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