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* Sink SubtargetFeature and TargetInstrItineraries (renamed ↵Evan Cheng2011-06-291-2/+1
| | | | | | MCInstrItineraries) into MC. llvm-svn: 134049
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-282-3/+3
| | | | llvm-svn: 134030
* Hide more details in tablegen generated MCRegisterInfo ctor function.Evan Cheng2011-06-281-2/+1
| | | | llvm-svn: 134027
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-285-5/+8
| | | | llvm-svn: 134024
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-282-4/+4
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Fix cmake build.Rafael Espindola2011-06-281-1/+1
| | | | llvm-svn: 133989
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-275-9/+10
| | | | | | into XXXGenRegisterInfo.inc. llvm-svn: 133922
* Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng2011-06-243-13/+14
| | | | | | | | | | | | target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. llvm-svn: 133782
* Use set operations instead of plain lists to enumerate register classes.Jakob Stoklund Olesen2011-06-151-27/+4
| | | | | | | | | | | | This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. llvm-svn: 133105
* Remove custom allocation order boilerplate that is no longer needed.Jakob Stoklund Olesen2011-06-091-23/+3
| | | | | | | | | | | | | | | | | | | | The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. llvm-svn: 132781
* Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher2011-06-081-11/+11
| | | | | | | | No functional change. Part of PR6965 llvm-svn: 132763
* Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola2011-05-302-0/+5
| | | | | | | | directives. Fixes PR9826. llvm-svn: 132317
* Remove DwarfRegNum from CARRY. I should be encoded with DW_OP_bit_piece.Rafael Espindola2011-05-271-1/+1
| | | | llvm-svn: 132190
* Fix some dwarf register numbers.Rafael Espindola2011-05-261-1/+1
| | | | llvm-svn: 132136
* Add missing mayLoad / mayStore flags to instruction definitions without ↵Cameron Zwarich2011-05-181-0/+5
| | | | | | | | patterns, which fixes all of the CodeGen/MBlaze verifier failures. llvm-svn: 131595
* Make the logic for determining function alignment more explicit. No ↵Eli Friedman2011-05-062-6/+2
| | | | | | functionality change. llvm-svn: 131012
* Remove some hard coded CR-LFs. Some of these were the entire files, one ofChandler Carruth2011-04-251-1/+1
| | | | | | | these was just one line of a file. Explicitly set the eol-style property on the files to try and ensure this fix stays. llvm-svn: 130125
* ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()Daniel Dunbar2011-04-192-16/+14
| | | | | | predicates. llvm-svn: 129816
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-152-4/+4
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Fix an error in the MBlaze delay slot filler.Wesley Peck2011-04-111-1/+1
| | | | llvm-svn: 129313
* Add scheduling information for the MBlaze backend.Wesley Peck2011-04-1116-228/+710
| | | | llvm-svn: 129311
* Don't crash on invalid instructions when disassembling MBlaze code.Wesley Peck2011-04-113-36/+115
| | | | | | This fixes http://llvm.org/bugs/show_bug.cgi?id=9653 llvm-svn: 129303
* We need to pass the TargetMachine object to the InstPrinter if we are printingBill Wendling2011-03-212-3/+5
| | | | | | | | | the alias of an InstAlias instead of the thing being aliased. Because we need to know the features that are valid for an InstAlias. This is part of a work-in-progress. llvm-svn: 127986
* Revert r124611 - "Keep track of incoming argument's location while emitting ↵Devang Patel2011-02-211-2/+2
| | | | | | | | | | | LiveIns." In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body. This requires some coordination with debugger to get this working. - The debugger needs to be aware of prolog_end attribute attached with line table entries. - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+) llvm-svn: 126155
* Use explicit add_subdirectory's for LLVM target sublibraries insteadOscar Fuentes2011-02-201-0/+5
| | | | | | | | | of testing for its presence at cmake time. This way the build automatically regenerates the makefiles when a svn update brings in a new sublibrary. llvm-svn: 126068
* Triple::MinGW64 is deprecated and removed. We can use Triple::MinGW32 generally.NAKAMURA Takumi2011-02-171-1/+0
| | | | | | No one uses *-mingw64. mingw-w64 is represented as {i686|x86_64}-w64-mingw32. In llvm side, i686 and x64 can be treated as similar way. llvm-svn: 125747
* MC/AsmParser: Add support for allowing the conversion process to fail (viaDaniel Dunbar2011-02-041-0/+2
| | | | | | custom conversion functions). llvm-svn: 124872
* Fix 80-column violations and whitespace.Bob Wilson2011-02-031-1/+2
| | | | llvm-svn: 124819
* Keep track of incoming argument's location while emitting LiveIns.Devang Patel2011-01-311-2/+2
| | | | llvm-svn: 124611
* Introduce virtual ParseRegister method in TargetAsmParser.Roman Divacky2011-01-271-4/+11
| | | | | | Create override of this method in X86/ARM/MBlaze. llvm-svn: 124378
* Add support for the --noexecstack option.Rafael Espindola2011-01-231-2/+4
| | | | llvm-svn: 124077
* Remove more duplicated code.Rafael Espindola2011-01-231-2/+2
| | | | llvm-svn: 124056
* Remove duplicated code.Rafael Espindola2011-01-231-2/+3
| | | | llvm-svn: 124054
* Teach frame lowering to ignore debug values after the terminators.Jakob Stoklund Olesen2011-01-131-1/+1
| | | | llvm-svn: 123399
* Fix merge falloutAnton Korobeynikov2011-01-101-2/+2
| | | | llvm-svn: 123172
* Update CMake stuffAnton Korobeynikov2011-01-101-1/+1
| | | | llvm-svn: 123171
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-107-33/+34
| | | | | | and fixes here and there. llvm-svn: 123170
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-4/+3
| | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. llvm-svn: 123044
* Remove dead code and silence warnings.Benjamin Kramer2011-01-061-4/+4
| | | | llvm-svn: 122957
* Commit 122778 broke DWARF debug output when using the MBlaze backend. Fixed ↵Wesley Peck2011-01-053-0/+30
| | | | | | by overriding TargetFrameInfo::getFrameIndexOffset to take into account the new frame index information. llvm-svn: 122889
* Fix more stack layout issues in the MBlaze backend.Wesley Peck2011-01-033-25/+40
| | | | llvm-svn: 122778
* Fix stack layout error in MBlaze backend.Wesley Peck2010-12-292-37/+98
| | | | llvm-svn: 122631
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-231-5/+5
| | | | llvm-svn: 122513
* Don't generate carry bit when loading immediate values on the Microblaze.Wesley Peck2010-12-222-2/+2
| | | | llvm-svn: 122385
* Add support for some of the LLVM atomic operations to the MBlaze backend.Wesley Peck2010-12-223-156/+386
| | | | llvm-svn: 122384
* Modeling the carry bit in the MSR register of the MicroBlaze.Wesley Peck2010-12-223-83/+140
| | | | llvm-svn: 122381
* Fix a regression introduced into the MBlaze delay slot filler.Wesley Peck2010-12-221-6/+25
| | | | llvm-svn: 122379
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-212-2/+2
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* Teach the MBlaze disassembler to disassemble special purpose registers.Wesley Peck2010-12-202-8/+11
| | | | llvm-svn: 122269
* Teach the MBlaze asm parser how to parse special purpose register names.Wesley Peck2010-12-204-38/+134
| | | | llvm-svn: 122261
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