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path: root/llvm/lib/Target/MBlaze/MBlazeInstrInfo.cpp
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* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-1/+1
| | | | | | since they are equivalent. llvm-svn: 155188
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Fix a couple of 80 column violations.Wesley Peck2011-09-231-1/+2
| | | | | | patch contributed by Jia Liu! llvm-svn: 140391
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-11/+0
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-1/+12
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-011-2/+2
| | | | llvm-svn: 134244
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-281-1/+2
| | | | llvm-svn: 134030
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-0/+2
| | | | llvm-svn: 134024
* Add scheduling information for the MBlaze backend.Wesley Peck2011-04-111-0/+2
| | | | llvm-svn: 129311
* Don't generate carry bit when loading immediate values on the Microblaze.Wesley Peck2010-12-221-1/+1
| | | | llvm-svn: 122385
* Teaching MBlaze backend how to reverse branch conditions.Wesley Peck2010-12-021-0/+30
| | | | llvm-svn: 120707
* Implement branch analysis in the MBlaze backend.Wesley Peck2010-11-211-4/+121
| | | | llvm-svn: 119951
* 1. Finishing MBlaze MC asm parser test casesWesley Peck2010-11-121-10/+10
| | | | | | | | | | 2. Parsing .word directive in MBlaze asm parser 3. Fixing hack where memory instructions reversed order of last two parameters 4. Fixing many improperly encoded instructions 5. Support parsing special instructions (MFS,MTS,etc.) 6. Removing unused functions from inst printer llvm-svn: 118941
* Adding initial AsmParser implementation for the MBlaze backend. It isWesley Peck2010-10-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-161-35/+0
| | | | llvm-svn: 108567
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-111-38/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. llvm-svn: 108099
* Replace copyRegToReg with copyPhysReg for MBlaze.Jakob Stoklund Olesen2010-07-111-8/+6
| | | | llvm-svn: 108079
* Use COPY in targetsJakob Stoklund Olesen2010-07-101-6/+2
| | | | llvm-svn: 108063
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-171-2/+3
| | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-3/+4
| | | | | | doesn't have to guess. llvm-svn: 103194
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-061-2/+4
| | | | llvm-svn: 103193
* No-ops emitted for scheduling don't correspond with anything in theDan Gohman2010-05-051-1/+0
| | | | | | user's source, so don't arbitrarily assign them a debug location. llvm-svn: 103121
* use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-10/+8
| | | | llvm-svn: 100214
* Adding the MicroBlaze backend.Wesley Peck2010-02-231-0/+222
The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. llvm-svn: 96969
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