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* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-302-38/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. llvm-svn: 274189
* Refactor and cleanup Assembly Parsing / LexingNirav Dave2016-06-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Recommiting after fixing non-atomic insert to front of SmallVector in MCAsmLexer.h Add explicit Comment Token in Assembly Lexing for future support for outputting explicit comments from inline assembly. As part of this, CPPHash Directives are now explicitly distinguished from Hash line comments in Lexer. Line comments are recorded as EndOfStatement tokens, not Comment tokens to simplify compatibility with current TargetParsers. This slightly complicates comment output. This remove all lexing tasks out of the parser, does minor cleanup to remove extraneous newlines Asm Output, and some improvements white space handling. Reviewers: rtrieu, dwmw2, rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D20009 llvm-svn: 273007
* Revert "Refactor and cleanup Assembly Parsing / Lexing"Nirav Dave2016-06-161-1/+1
| | | | | | | | Reverting for unexpected crashes on various platforms. This reverts commit r272953. llvm-svn: 272957
* Refactor and cleanup Assembly Parsing / LexingNirav Dave2016-06-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Add explicit Comment Token in Assembly Lexing for future support for outputting explicit comments from inline assembly. As part of this, CPPHash Directives are now explicitly distinguished from Hash line comments in Lexer. Line comments are recorded as EndOfStatement tokens, not Comment tokens to simplify compatibility with current TargetParsers. This slightly complicates comment output. This remove all lexing tasks out of the parser, does minor cleanup to remove extraneous newlines Asm Output, and some improvements white space handling. Reviewers: rtrieu, dwmw2, rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D20009 llvm-svn: 272953
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-127-28/+30
| | | | | | | | This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. llvm-svn: 272512
* [lanai] Change reloc to use PIC_ by default and cleanup.Jacques Pienaar2016-05-206-15/+20
| | | | | | | * Change reloc to PIC_; * Cleanup (clang-format & modify test); llvm-svn: 270282
* [lanai] Use Optional<Reloc> in LanaiTargetMachine.Jacques Pienaar2016-05-204-12/+17
| | | | | | Follow r269988 and use Optional<Reloc>. llvm-svn: 270176
* [lanai] Change the way flag setting instructions are checked.Jacques Pienaar2016-05-181-51/+11
| | | | | | | | isReturn() was returning different values with and without -g which led to different code being generated. Change isFlagSettingInstruction to query an instruction's effect on SR instead. llvm-svn: 269986
* SDAG: Implement Select instead of SelectImpl in LanaiDAGToDAGISelJustin Bogner2016-05-121-21/+13
| | | | | | | | | - Where we were returning a node before, call ReplaceNode instead. - Where we were calling SelectNodeTo, just return afterwards. Part of llvm.org/pr26808. llvm-svn: 269364
* CodeGen: Move TargetPassConfig from Passes.h to an own header; NFCMatthias Braun2016-05-101-0/+1
| | | | | | | | Many files include Passes.h but only a fraction needs to know about the TargetPassConfig class. Move it into an own header. Also rename Passes.cpp to TargetPassConfig.cpp while we are at it. llvm-svn: 269011
* SDAG: Rename Select->SelectImpl and repurpose Select as returning voidJustin Bogner2016-05-051-2/+2
| | | | | | | | | | | | | | This is a step towards removing the rampant undefined behaviour in SelectionDAG, which is a part of llvm.org/PR26808. We rename SelectionDAGISel::Select to SelectImpl and update targets to match, and then change Select to return void and consolidate the sketchy behaviour we're trying to get away from there. Next, we'll update backends to implement `void Select(...)` instead of SelectImpl and eventually drop the base Select implementation. llvm-svn: 268693
* [CodeGen] Default CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF to Expand in ↵Craig Topper2016-04-281-2/+0
| | | | | | TargetLoweringBase. This is what the majority of the targets want and removes a bunch of code. Set it to Legal explicitly in the few cases where that's the desired behavior. llvm-svn: 267853
* Remove MinLatency in SchedMachineModel. NFC.Junmo Park2016-04-261-4/+0
| | | | | | | | | | | Summary: We don't use MinLatency any more since r184032. Reviewers: atrick, hfinkel, mcrosier Differential Revision: http://reviews.llvm.org/D19474 llvm-svn: 267502
* [lanai] Expand findClosestSuitableAluInstr check to consider offset register.Jacques Pienaar2016-04-251-3/+6
| | | | | | Previously findClosestSuitableAluInstr was only considering the base register when checking the current instruction for suitability. Expand check to consider the offset if the offset is a register. llvm-svn: 267424
* [Lanai] Use EVT::getEVTString() to print a type as a string instead of an ↵Craig Topper2016-04-241-1/+1
| | | | | | enum encoding value. llvm-svn: 267348
* [Lanai] Set CTLZ_ZERO_UNDEF/CTTZ_ZERO_UNDEF to Expand instead of Legal so ↵Craig Topper2016-04-222-11/+2
| | | | | | they will be converted to CTLZ/CTTZ by LegalizeDAG. Remove extra instructions that only existed to to contain patterns that match the zero_undef operations. NFC llvm-svn: 267108
* [Lanai] Remove unused methods declarations. NFCCraig Topper2016-04-221-3/+0
| | | | llvm-svn: 267107
* [lanai] Add subword scheduling itineraries.Jacques Pienaar2016-04-202-17/+34
| | | | | | | | Differentiate between word and subword memory operations as they take different amount of cycles to complete. This just adds a basic model of the subword latency to the scheduler. llvm-svn: 266898
* [lanai] Add lowering for SETCCE i32.Jacques Pienaar2016-04-193-34/+68
| | | | | | | | * Add lowering for SETCCE i32. * Add test to check lowering of i64 compares uses SETCCE expansion (outside of EQ and NE). * Fix select.ll test and immediate form selection for RI operations. llvm-svn: 266802
* [lanai] Set boolean contentss to ZeroOrOneBooleanContent.Jacques Pienaar2016-04-191-0/+3
| | | | llvm-svn: 266701
* Lanai: fix debug buildJF Bastien2016-04-181-1/+1
| | | | | | There's currently no raw_ostream &operator<<(SimpleValueType); provided by LLVM. It could be added by refactoring utils/TableGen/CodeGenTarget.cpp:getEnumName, but that's much more work than fixing the build. llvm-svn: 266627
* [NFC] Header cleanupMehdi Amini2016-04-181-1/+0
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* [lanai] Add custom lowering for SRL_PARTS i32.Jacques Pienaar2016-04-142-1/+44
| | | | llvm-svn: 266349
* [lanai] Add areMemAccessesTriviallyDisjoint, getMemOpBaseRegImmOfs and ↵Jacques Pienaar2016-04-142-2/+103
| | | | | | | | | | | | | | getMemOpBaseRegImmOfsWidth. Summary: Add getMemOpBaseRegImmOfsWidth to enable determining independence during MiSched. Reviewers: eliben, majnemer Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18903 llvm-svn: 266338
* [lanai] LanaiSetflagAluCombiner more conservativeJacques Pienaar2016-04-051-5/+7
| | | | | | | | | | | | Summary: LanaiSetflagAluCombiner could previously combine instructions across basic building blocks even when not legal. Make the LanaiSetflagAluCombiner more conservative to avoid this. Reviewers: eliben Subscribers: joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D18746 llvm-svn: 265411
* Lanai: fix -Wsign-compare warningJF Bastien2016-04-051-1/+1
| | | | llvm-svn: 265368
* Lanai: fix -Wpedantic warningsJF Bastien2016-04-042-2/+2
| | | | | | Extra semicolon. llvm-svn: 265365
* Add MachineFunctionProperty checks for AllVRegsAllocated for target passesDerek Schuff2016-04-043-0/+15
| | | | | | | | | | | | | | Summary: This adds the same checks that were added in r264593 to all target-specific passes that run after register allocation. Reviewers: qcolombet Subscribers: jyknight, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18525 llvm-svn: 265313
* [lanai] Fix for LanaiDelaySlotFiller and LanaiMCInstLower.cppJacques Pienaar2016-04-033-104/+87
| | | | | | | | | | | | | Summary: * Fix to stop delay slot filler from inserting SP modifying instructions in the newly expanded call/return instructions. * In LowerSymbol the outermost type was not LanaiMCExpr if there was a binary expression * Remove printExpr in LanaiInstPrinter Subscribers: joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D18734 llvm-svn: 265251
* Change eliminateCallFramePseudoInstr() to return an iteratorHans Wennborg2016-03-312-3/+3
| | | | | | | | | | | | | | | | | | | | | This will become necessary in a subsequent change to make this method merge adjacent stack adjustments, i.e. it might erase the previous and/or next instruction. It also greatly simplifies the calls to this function from Prolog- EpilogInserter. Previously, that had a bunch of logic to resume iteration after the call; now it just continues with the returned iterator. Note that this changes the behaviour of PEI a little. Previously, it attempted to re-visit the new instruction created by eliminateCallFramePseudoInstr(). That code was added in r36625, but I can't see any reason for it: the new instructions will obviously not be pseudo instructions, they will not have FrameIndex operands, and we have already accounted for the stack adjustment. Differential Revision: http://reviews.llvm.org/D18627 llvm-svn: 265036
* [lanai] isBrImm should accept any non-constant immediate.Jacques Pienaar2016-03-311-17/+6
| | | | | | | | isBrImm should accept any non-constant immediate. Previously it was only accepting LanaiMCExpr ones which was wrong. Differential Revision: http://reviews.llvm.org/D18571 llvm-svn: 265032
* [lanai] Add Lanai backend.Jacques Pienaar2016-03-2864-0/+10073
Add the Lanai backend to lib/Target. General Lanai backend discussion on llvm-dev thread "[RFC] Lanai backend" (http://lists.llvm.org/pipermail/llvm-dev/2016-February/095118.html). Differential Revision: http://reviews.llvm.org/D17011 llvm-svn: 264578
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