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* just some random hacking - calls (particularly indirect) need a lot ofDuraid Madina2005-11-061-14/+25
| | | | | | love (especially with -sched=simple) llvm-svn: 24225
* ask for 16-byte aligned jmpbufs. This should unbreak C++ on IA64 (andDuraid Madina2005-11-061-1/+2
| | | | | | | a bunch of other things) but is currently ignored by the code generator. llvm-svn: 24206
* oops, forgot to load GP for indirect calls, though the old code now commentedDuraid Madina2005-11-041-4/+21
| | | | | | | | | out failed (e.g. methcall) - now the code compiles, though it's not quite right just yet (tm) ;) would fix this but it's 3am! :O llvm-svn: 24186
* kill redundant SP/GP/RP save/restores across callsDuraid Madina2005-11-041-2/+3
| | | | llvm-svn: 24183
* add support for loading boolsDuraid Madina2005-11-041-1/+7
| | | | llvm-svn: 24182
* fun with predicates! (add TRUNC i64->i1, AND i1 i1, fix XOR i1 i1)Duraid Madina2005-11-041-41/+97
| | | | llvm-svn: 24175
* add pattern to load constant 0 into a predicate regDuraid Madina2005-11-031-0/+2
| | | | llvm-svn: 24164
* Fix a bug that prevented this pattern from matchingChris Lattner2005-11-031-1/+1
| | | | llvm-svn: 24161
* "fix" support for FP constants (this code asserts in the scheduler,Duraid Madina2005-11-021-2/+4
| | | | | | though) llvm-svn: 24152
* add F0 and F1 to the FP register classDuraid Madina2005-11-021-3/+19
| | | | llvm-svn: 24151
* This works nowChris Lattner2005-11-021-2/+1
| | | | llvm-svn: 24150
* add support for SELECT to TargetSelectionDAG.td, add support forDuraid Madina2005-11-021-31/+38
| | | | | | selecting ints to IA64, and a few other ia64 bits and pieces llvm-svn: 24147
* add support for loading FP constants +0.0 and +1.0 to the dag isel,Duraid Madina2005-11-022-3/+8
| | | | | | stop pretending -0.0 and -1.0 are machine constants llvm-svn: 24146
* heh, scheduling was easy?Duraid Madina2005-11-011-1/+3
| | | | | | need to send chris, jim and sampo a box of fish each llvm-svn: 24135
* FORTRAN!!! :( and other similarly unfortunate things mean that on ia64Duraid Madina2005-11-011-0/+20
| | | | | | one sometimes needs to pass FP args in both FP *and* integer registers. llvm-svn: 24134
* so tablegen was thinking I might want to convert FPs to predicates.Duraid Madina2005-11-011-4/+3
| | | | | | clever little tablegen! llvm-svn: 24133
* add support for int->FP and FP->int ops, and add ia64 patterns for theseDuraid Madina2005-11-011-0/+12
| | | | llvm-svn: 24132
* add zeroextend predicate->integerDuraid Madina2005-11-011-37/+42
| | | | llvm-svn: 24131
* add FP compares and implicit register defs to the dag iselDuraid Madina2005-10-312-23/+45
| | | | llvm-svn: 24118
* fix some broken comparisons, this affected the Pattern isel too.Duraid Madina2005-10-301-27/+4
| | | | llvm-svn: 24109
* add some FP stuff, some mix.* stuff, and constant pool support to theDuraid Madina2005-10-292-61/+131
| | | | | | | DAG instruction selector, which should be destroyed one day (in the pattern isel also) since ia64 can pack any constant in the instruction stream llvm-svn: 24094
* add shladdDuraid Madina2005-10-291-42/+42
| | | | llvm-svn: 24080
* These are autogeneratedChris Lattner2005-10-281-33/+0
| | | | llvm-svn: 24063
* DAG->DAG instruction selection for ia64! "hello world" works, not much else.Duraid Madina2005-10-2811-41/+1226
| | | | | | | | | | | | | | | | | | | | | use -enable-ia64-dag-isel to turn this on TODO: delete lowering stuff from the pattern isel : get operations on predicate bits working : get other bits of pseudocode going : use sampo's mulh/mull-using divide-by-constant magic : *so* many patterns ("extr", "tbit" and "dep" will be fun :) : add FP : add a JIT! : get it working 100% in short: this'll be happier in a couple of weeks, but it's here now so the tester can make me feel guilty sooner. OTHER: there are a couple of fixes to the pattern isel, in particular making the linker happy with big blobs of fun like pypy. llvm-svn: 24058
* remove dead stuffChris Lattner2005-10-281-14/+0
| | | | llvm-svn: 24054
* Eliminate getClass, it is not neededChris Lattner2005-10-281-7/+6
| | | | llvm-svn: 24053
* Don't generate operations that aren't yet supportedNate Begeman2005-10-211-1/+4
| | | | llvm-svn: 23858
* Fix CodeGen/Generic/bool-to-double.llChris Lattner2005-10-071-0/+3
| | | | llvm-svn: 23652
* these registers don't belong to any register classes, so don't mark themChris Lattner2005-09-301-11/+21
| | | | | | as callee save. They can never be generated by the compiler. llvm-svn: 23551
* these methods get extra argsChris Lattner2005-09-302-6/+10
| | | | llvm-svn: 23538
* Add FP versions of the binary operators, keeping the int and fp worlds seperate.Chris Lattner2005-09-281-58/+65
| | | | | | | | Though I have done extensive testing, it is possible that this will break things in configs I can't test. Please let me know if this causes a problem and I'll fix it ASAP. llvm-svn: 23505
* Give all operands namesChris Lattner2005-09-141-1/+1
| | | | llvm-svn: 23357
* ignore generated filesChris Lattner2005-09-071-0/+1
| | | | llvm-svn: 23263
* Handle ANY_EXTEND like ZERO_EXTEND. Simplify the extend/truncate code onChris Lattner2005-09-021-59/+23
| | | | | | the observation that it only has to handle i1 -> i64 and i64 -> i1. llvm-svn: 23201
* 1. Use SubtargetFeatures in llc/lli.Jim Laskey2005-09-012-2/+4
| | | | | | | | 2. Propagate feature "string" to all targets. 3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget. llvm-svn: 23192
* Fix a bug in my previous checkinChris Lattner2005-08-261-1/+1
| | | | llvm-svn: 23082
* Change ConstantPoolSDNode to actually hold the Constant itself instead ofChris Lattner2005-08-261-2/+5
| | | | | | | | putting it into the constant pool. This allows the isel machinery to create constants that it will end up deciding are not needed, without them ending up in the resultant function constant pool. llvm-svn: 23081
* fix a warning in optimized buildChris Lattner2005-08-251-1/+1
| | | | llvm-svn: 23030
* Fix a crash I introduced into the IA64 backend with my copyfromreg change.Chris Lattner2005-08-221-1/+3
| | | | | | It used to crash on any function that took float arguments. llvm-svn: 22973
* Add a pass name for -time-passes outputChris Lattner2005-08-221-0/+1
| | | | llvm-svn: 22970
* reenable collapse of loadimm+AND -> dep.z (thanks guys)Duraid Madina2005-08-211-5/+6
| | | | llvm-svn: 22944
* Repair an out by one error for IA64.Jim Laskey2005-08-201-1/+1
| | | | llvm-svn: 22942
* Split RegisterClass 'Methods' into MethodProtos and MethodBodiesChris Lattner2005-08-191-4/+9
| | | | llvm-svn: 22929
* Put register classes in namespacesChris Lattner2005-08-191-3/+3
| | | | llvm-svn: 22924
* This code has always been dead on itaniumChris Lattner2005-08-192-22/+0
| | | | llvm-svn: 22916
* a bugfix (up top) and a quick repair job: disable generation of dep.zDuraid Madina2005-08-191-3/+3
| | | | | | | | (which died about a week ago) so we're back to load-(2^n-1)-then-AND sequences. slow, but things should now be Almost Completely Working, modulo those pesky alignment/ABI issues. llvm-svn: 22904
* Mark some instructions as variable_ops, and PSEUDO_ALLOC as taking a GPR.Chris Lattner2005-08-191-7/+8
| | | | | | | I'm not convinced this is all of them, but I can't do much testing, because IA64 LLC crashes on big programs :( llvm-svn: 22892
* update the backends to work with the new CopyFromReg/CopyToReg/ImplicitDef nodesChris Lattner2005-08-161-9/+12
| | | | llvm-svn: 22807
* Implement BR_CC and BRTWOWAY_CC. This allows the removal of a rather nastyNate Begeman2005-08-161-0/+1
| | | | | | | fixme from the PowerPC backend. Emit slightly better code for legalizing select_cc. llvm-svn: 22805
* sorry!! this is temporary; for some reason the nasty constmul code seems toDuraid Madina2005-08-101-3/+4
| | | | | | | be an infinite loop when using g++-4.0.1*, this kills the ia64 nightly tester. A proper fix shall be forthcoming!!! thanks for not killing me. :) llvm-svn: 22748
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