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* fix some 80-col violationsGabor Greif2008-08-302-3/+5
| | | | llvm-svn: 55565
* erect abstraction boundaries for accessing SDValue members, rename Val -> ↵Gabor Greif2008-08-282-7/+7
| | | | | | Node to reflect semantics llvm-svn: 55504
* Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy ↵Owen Anderson2008-08-262-4/+6
| | | | | | | | | requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
* Move the point at which FastISel taps into the SelectionDAGISelDan Gohman2008-08-231-3/+3
| | | | | | | | | | | | | | | | | | process up to a higher level. This allows FastISel to leverage more of SelectionDAGISel's infastructure, such as updating Machine PHI nodes. Also, implement transitioning from SDISel back to FastISel in the middle of a block, so it's now possible to go back and forth. This allows FastISel to hand individual CallInsts and other complicated things off to SDISel to handle, while handling the rest of the block itself. To help support this, reorganize the SelectionDAG class so that it is allocated once and reused throughout a function, instead of being completely reallocated for each block. llvm-svn: 55219
* Simplify SelectRoot's interface, and factor out some common codeDan Gohman2008-08-211-1/+1
| | | | | | from all targets. llvm-svn: 55124
* Use raw_ostream throughout the AsmPrinter.Owen Anderson2008-08-214-6/+8
| | | | llvm-svn: 55092
* Convert uses of std::vector in TargetInstrInfo to SmallVector. This change ↵Owen Anderson2008-08-142-2/+2
| | | | | | had to be propoagated down into all the targets and up into all clients of this API. llvm-svn: 54802
* Handle visibility printing with all generality. Remove bunch of duplicate code.Anton Korobeynikov2008-08-081-1/+4
| | | | llvm-svn: 54540
* Use EmitAlignment consistentlyAnton Korobeynikov2008-08-071-1/+1
| | | | llvm-svn: 54456
* CleanupAnton Korobeynikov2008-08-071-9/+9
| | | | llvm-svn: 54454
* Switch IA64 to new section-handling stuffAnton Korobeynikov2008-08-073-71/+90
| | | | llvm-svn: 54453
* CleanupAnton Korobeynikov2008-08-071-18/+16
| | | | llvm-svn: 54452
* Rename SDOperand to SDValue.Dan Gohman2008-07-273-137/+137
| | | | llvm-svn: 54128
* Add a new function, ReplaceAllUsesOfValuesWith, which handles bulkDan Gohman2008-07-171-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | replacement of multiple values. This is slightly more efficient than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically could be optimized even further. However, an important property of this new function is that it handles the case where the source value set and destination value set overlap. This makes it feasible for isel to use SelectNodeTo in many very common cases, which is advantageous because SelectNodeTo avoids a temporary node and it doesn't require CSEMap updates for users of values that don't change position. Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to handle operand lists more efficiently, and to correctly handle a number of corner cases to which its new wider use exposes it. This commit also includes a change to the encoding of post-isel opcodes in SDNodes; now instead of being sandwiched between the target-independent pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel opcodes are now represented as negative values. This makes it possible to test if an opcode is pre-isel or post-isel without having to know the size of the current target's post-isel instruction set. These changes speed up llc overall by 3% and reduce memory usage by 10% on the InstructionCombining.cpp testcase with -fast and -regalloc=local. llvm-svn: 53728
* random bugfix sitting in my tree.Chris Lattner2008-07-091-1/+2
| | | | llvm-svn: 53274
* Pool-allocation for MachineInstrs, MachineBasicBlocks, andDan Gohman2008-07-072-39/+25
| | | | | | | | | | | MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
* Add explicit keywords.Dan Gohman2008-07-071-1/+1
| | | | llvm-svn: 53179
* Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman2008-07-011-1/+2
| | | | | | | | | | | | | | | | the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. llvm-svn: 52943
* Rename ISD::LOCATION to ISD::DBG_STOPPOINT to better reflect itsDan Gohman2008-06-301-1/+1
| | | | | | | | | | | | | | | | | purpose, and give it a custom SDNode subclass so that it doesn't need to have line number, column number, filename string, and directory string, all existing as individual SDNodes to be the operands. This was the only user of ISD::STRING, StringSDNode, etc., so remove those and some associated code. This makes stop-points considerably easier to read in -view-legalize-dags output, and reduces overhead (creating new nodes and copying std::strings into them) on code containing debugging information. llvm-svn: 52924
* Split scheduling from instruction selection.Evan Cheng2008-06-301-7/+4
| | | | llvm-svn: 52923
* Replace some std::vectors that showed up in heap profiling withDan Gohman2008-06-302-7/+4
| | | | | | | | SmallVectors. Change the signature of TargetLowering::LowerArguments to avoid returning a vector by value, and update the two targets which still use this directly, Sparc and IA64, accordingly. llvm-svn: 52917
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-063-22/+21
| | | | | | | | | | | | | | | | and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
* Update some comments noticed in a recent checkinNate Begeman2008-05-281-3/+8
| | | | llvm-svn: 51644
* Add chain inputs for loads.Chris Lattner2008-05-281-3/+3
| | | | llvm-svn: 51635
* Fix CodeGen/Generic/2005-10-21-longlonggtu.ll on ia64.Chris Lattner2008-05-281-1/+2
| | | | llvm-svn: 51634
* loads should get chains. THis helps but does not solve ↵Chris Lattner2008-05-281-2/+4
| | | | | | | | CodeGen/Generic/2003-05-27-phifcmpd.ll on ia64. llvm-svn: 51633
* Fix 2006-04-28-Sign-extend-bool.ll for ia64.Chris Lattner2008-05-281-0/+2
| | | | llvm-svn: 51632
* reindent.Chris Lattner2008-05-281-77/+77
| | | | llvm-svn: 51631
* Add CommonLinkage; currently tentative definitionsDale Johannesen2008-05-141-0/+2
| | | | | | | | | | are represented as "weak", but there are subtle differences in some cases on Darwin, so we need both. The intent is that "common" will behave identically to "weak" unless somebody changes their target to do something else. No functional change as yet. llvm-svn: 51118
* Change target-specific classes to use more precise static types.Dan Gohman2008-05-142-2/+2
| | | | | | | This eliminates the need for several awkward casts, including the last dynamic_cast under lib/Target. llvm-svn: 51091
* Clean up the use of static and anonymous namespaces. This turned upDan Gohman2008-05-131-3/+1
| | | | | | | several things that were neither in an anonymous namespace nor static but not intended to be global. llvm-svn: 51017
* Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not LegalDan Gohman2008-04-121-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | on any current target and aren't optimized in DAGCombiner. Instead of using intermediate nodes, expand the operations, choosing between simple loads/stores, target-specific code, and library calls, immediately. Previously, the code to emit optimized code for these operations was only used at initial SelectionDAG construction time; now it is used at all times. This fixes some cases where rep;movs was being used for small copies where simple loads/stores would be better. This also cleans up code that checks for alignments less than 4; let the targets make that decision instead of doing it in target-independent code. This allows x86 to use rep;movs in low-alignment cases. Also, this fixes a bug that resulted in the use of rep;stos for memsets of 0 with non-constant memory size when the alignment was at least 4. It's better to use the library in this case, which can be significantly faster when the size is large. This also preserves more SourceValue information when memory intrinsics are lowered into simple loads/stores. llvm-svn: 49572
* Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.Evan Cheng2008-03-312-12/+0
| | | | llvm-svn: 48995
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-151-11/+0
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. llvm-svn: 48380
* Use SDTNone instead of duplicating it.Dan Gohman2008-03-131-2/+1
| | | | llvm-svn: 48346
* Use PassManagerBase instead of FunctionPassManager for functionsDan Gohman2008-03-112-6/+6
| | | | | | | | that merely add passes. This allows them to be used with either FunctionPassManager or PassManager, or even with a custom new kind of pass manager. llvm-svn: 48256
* - Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency.Scott Michel2008-03-101-1/+3
| | | | | | | - Add test pattern matching in CellSPU's icmp32.ll test harness - Fix CellSPU fcmp.ll-generated assert. llvm-svn: 48197
* Default ISD::PREFETCH to expand.Evan Cheng2008-03-101-1/+0
| | | | llvm-svn: 48169
* Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC'sScott Michel2008-03-102-1/+5
| | | | | | | | return ValueType can depend its operands' ValueType. This is a cosmetic change, no functionality impacted. llvm-svn: 48145
* make sure ar.pfs is in a register class, this fixes test/CodeGen/IA64/ret-0.llChris Lattner2008-03-091-3/+5
| | | | llvm-svn: 48118
* Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} ↵Evan Cheng2008-03-081-0/+1
| | | | | | and prefetchnta instructions. llvm-svn: 48042
* Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to ↵Evan Cheng2008-02-281-1/+1
| | | | | | 16-byte boundaries. llvm-svn: 47703
* Final de-tabification.Bill Wendling2008-02-272-80/+79
| | | | llvm-svn: 47663
* Change "Name" to "AsmName" in the target register info. Gee, a refactoring toolBill Wendling2008-02-261-2/+2
| | | | | | would have been a Godsend here! llvm-svn: 47625
* De-tabifyBill Wendling2008-02-261-2/+0
| | | | llvm-svn: 47600
* Remove bunch of gcc 4.3-related warnings from TargetAnton Korobeynikov2008-02-201-2/+0
| | | | llvm-svn: 47369
* I cannot find a libgcc function for this builtin. Therefor expanding it to ↵Andrew Lenharth2008-02-161-1/+2
| | | | | | a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support. llvm-svn: 47213
* In TargetLowering::LowerCallTo, don't assert thatDuncan Sands2008-02-142-5/+6
| | | | | | | | | | | | | | | | | the return value is zero-extended if it isn't sign-extended. It may also be any-extended. Also, if a floating point value was returned in a larger floating point type, pass 1 as the second operand to FP_ROUND, which tells it that all the precision is in the original type. I think this is right but I could be wrong. Finally, when doing libcalls, set isZExt on a parameter if it is "unsigned". Currently isSExt is set when signed, and nothing is set otherwise. This should be right for all calls to standard library routines. llvm-svn: 47122
* Change how FP immediates are handled. Nate Begeman2008-02-142-3/+19
| | | | | | | | | | | | | | 1) ConstantFP is now expand by default 2) ConstantFP is not turned into TargetConstantFP during Legalize if it is legal. This allows ConstantFP to be handled like Constant, allowing for targets that can encode FP immediates as MachineOperands. As a bonus, fix up Itanium FP constants, which now correctly match, and match more constants! Hooray. llvm-svn: 47121
* Stuff noticed while grepping codeNate Begeman2008-02-111-65/+7
| | | | llvm-svn: 46979
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