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* [RDF] Extract the physical register information into a separate classKrzysztof Parzyszek2017-01-307-254/+344
| | | | llvm-svn: 293510
* [RDF] Add phis for entry block live-ins (in addition to function live-ins)Krzysztof Parzyszek2017-01-303-14/+22
| | | | llvm-svn: 293491
* [Hexagon] Make header self-contained.Benjamin Kramer2017-01-301-0/+3
| | | | llvm-svn: 293482
* Cleanup dump() functions.Matthias Braun2017-01-282-2/+4
| | | | | | | | | | | | | | | | | | We had various variants of defining dump() functions in LLVM. Normalize them (this should just consistently implement the things discussed in http://lists.llvm.org/pipermail/cfe-dev/2014-January/034323.html For reference: - Public headers should just declare the dump() method but not use LLVM_DUMP_METHOD or #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) - The definition of a dump method should look like this: #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) LLVM_DUMP_METHOD void MyClass::dump() { // print stuff to dbgs()... } #endif llvm-svn: 293359
* [Hexagon] Remove unused variable (and silence a warning)Krzysztof Parzyszek2017-01-271-4/+2
| | | | llvm-svn: 293331
* [Hexagon] Require IPO library in Hexagon buildKrzysztof Parzyszek2017-01-261-0/+1
| | | | | | This should unbreak the Hexagon build bots. llvm-svn: 293221
* [Hexagon] Add Hexagon-specific loop idiom recognition passKrzysztof Parzyszek2017-01-264-5/+1637
| | | | llvm-svn: 293213
* Add iterator_range<regclass_iterator> to {Target,MC}RegisterInfo, NFCKrzysztof Parzyszek2017-01-251-2/+1
| | | | llvm-svn: 293077
* [RDF] Add registers to live set even if they are live alreadyKrzysztof Parzyszek2017-01-231-6/+5
| | | | | | | | When calculating kills, a register may be considered live because a part of it is live, but if there is a use of that (whole) register, the whole register (and its subregisters) need to be added to the live set. llvm-svn: 292845
* [Hexagon] Explicitly reserve aliases of reserved registersKrzysztof Parzyszek2017-01-232-13/+22
| | | | llvm-svn: 292836
* [Hexagon] Remove dead defs from the live set when expanding wstoresKrzysztof Parzyszek2017-01-181-1/+8
| | | | llvm-svn: 292445
* "Use" lambda captures which are otherwise only used in asserts. NFCDavid L. Jones2017-01-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: The LLVM coding standards recommend "using" values that are only needed by asserts: http://llvm.org/docs/CodingStandards.html#assert-liberally Without this change, LLVM cannot bootstrap with -Werror as the second stage fails with this new warning: https://reviews.llvm.org/rL291905 See also the previous fixes: https://reviews.llvm.org/rL291916 https://reviews.llvm.org/rL291939 https://reviews.llvm.org/rL291940 https://reviews.llvm.org/rL291941 Reviewers: rsmith Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28695 llvm-svn: 291957
* Remove unused lambda captures. NFCMalcolm Parsons2017-01-133-5/+5
| | | | llvm-svn: 291916
* [CodeGen] Rename MachineInstrBuilder::addOperand. NFCDiana Picus2017-01-138-65/+62
| | | | | | | | | | | Rename from addOperand to just add, to match the other method that has been added to MachineInstrBuilder for adding more than just 1 operand. See https://reviews.llvm.org/D28057 for the whole discussion. Differential Revision: https://reviews.llvm.org/D28556 llvm-svn: 291891
* [Hexagon, TableGen] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-01-0412-385/+301
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 290925
* [Hexagon] Add DAG mutations for machine pipelinerKrzysztof Parzyszek2016-12-222-0/+9
| | | | llvm-svn: 290366
* Fix build with expensive checks enabledSerge Pavlov2016-12-201-0/+1
| | | | | | | | | Include of llvm/IR/Verifier.h was removed from HexagonCommonGEP.cpp in r289604 as unused. In fact it is required when expensive checks are enabled, because it declared function `verifyFunction`, which is called in conditionally compiled part of the file. llvm-svn: 290170
* [Hexagon] Restore minimum profit check accidentally changed in r290024Malcolm Parsons2016-12-191-2/+2
| | | | llvm-svn: 290100
* [Hexagon] Other attempt to fix build with enabled asserts broken in 290024 ↵Eugene Zelenko2016-12-171-0/+1
| | | | | | (NFC). llvm-svn: 290028
* [Hexagon] Fix build with enabled asserts broken in 290024 (NFC).Eugene Zelenko2016-12-171-0/+1
| | | | llvm-svn: 290027
* [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2016-12-1711-163/+220
| | | | | | other minor fixes (NFC). llvm-svn: 290024
* Implement LaneBitmask::any(), use it to replace !none(), NFCIKrzysztof Parzyszek2016-12-165-11/+11
| | | | llvm-svn: 289974
* [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2016-12-166-151/+235
| | | | | | other minor fixes (NFC). llvm-svn: 289907
* Extract LaneBitmask into a separate typeKrzysztof Parzyszek2016-12-155-24/+24
| | | | | | | | | | | | Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
* [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2016-12-145-284/+249
| | | | | | other minor fixes (NFC). llvm-svn: 289736
* [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2016-12-137-402/+359
| | | | | | other minor fixes (NFC). llvm-svn: 289604
* [RDF] Fix incorrect lane mask calculationKrzysztof Parzyszek2016-12-081-7/+31
| | | | | | | | This was exposed by some code that used more than one level of sub- registers. There is no testcase, because there is no such code in the Hexagon backend. llvm-svn: 289099
* [Hexagon] Adding additional tokenization characters in preparation for ↵Colin LeMahieu2016-12-053-8/+2
| | | | | | removing spacing from syntax. llvm-svn: 288637
* [Hexagon] Changing from literal numeric value to argument since #-1 will not ↵Colin LeMahieu2016-12-056-21/+56
| | | | | | parse when '-' is converted to a token. llvm-svn: 288634
* IR: Change PointerType to derive from Type rather than SequentialType.Peter Collingbourne2016-12-021-0/+2
| | | | | | | | | | | | | | | | | | | As proposed on llvm-dev: http://lists.llvm.org/pipermail/llvm-dev/2016-October/106640.html This is for a couple of reasons: - Values of type PointerType are unlike the other SequentialTypes (arrays and vectors) in that they do not hold values of the element type. By moving PointerType we can unify certain aspects of how the other SequentialTypes are handled. - PointerType will have no place in the SequentialType hierarchy once pointee types are removed, so this is a necessary step towards removing pointee types. Differential Revision: https://reviews.llvm.org/D26595 llvm-svn: 288462
* Move FrameInstructions from MachineModuleInfo to MachineFunctionMatthias Braun2016-11-301-6/+6
| | | | | | | | | | | This is per function data so it is better kept at the function instead of the module. This is a necessary step to have machine module passes work properly. Differential Revision: https://reviews.llvm.org/D27185 llvm-svn: 288291
* Check that emitted instructions meet their predicates on all targets except ↵Daniel Sanders2016-11-192-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | ARM, Mips, and X86. Summary: * ARM is omitted from this patch because this check appears to expose bugs in this target. * Mips is omitted from this patch because this check either detects bugs or deliberate emission of instructions that don't satisfy their predicates. One deliberate use is the SYNC instruction where the version with an operand is correctly defined as requiring MIPS32 while the version without an operand is defined as an alias of 'SYNC 0' and requires MIPS2. * X86 is omitted from this patch because it doesn't use the tablegen-erated MCCodeEmitter infrastructure. Patches for ARM and Mips will follow. Depends on D25617 Reviewers: tstellarAMD, jmolloy Subscribers: wdng, jmolloy, aemerson, rengolin, arsenm, jyknight, nemanjai, nhaehnle, tstellarAMD, llvm-commits Differential Revision: https://reviews.llvm.org/D25618 llvm-svn: 287439
* Timer: Track name and description.Matthias Braun2016-11-183-7/+10
| | | | | | | | | | | | | The previously used "names" are rather descriptions (they use multiple words and contain spaces), use short programming language identifier like strings for the "names" which should be used when exporting to machine parseable formats. Also removed a unused TimerGroup from Hexxagon. Differential Revision: https://reviews.llvm.org/D25583 llvm-svn: 287369
* Fix spelling mistakes in Hexagon target comments. NFC.Simon Pilgrim2016-11-179-12/+12
| | | | | | Identified by Pedro Giffuni in PR27636. llvm-svn: 287248
* [Hexagon] Give a predicate function a more meaningful nameKrzysztof Parzyszek2016-11-142-18/+18
| | | | | | | Change "orisadd" to "IsOrAdd" to follow the naming conventions, and change "isOrAdd" in the C++ code to "isOrEquivalentToAdd". llvm-svn: 286886
* [Hexagon] Remove unsafe load instructions that affect Stack Slot ColoringSumanth Gundapaneni2016-11-141-12/+0
| | | | | | | | | | | | | | | | | The Stack slot coloring pass removes a store that is followed by a load that deal with the same stack slot. The function isLoadFromStackSlot is supposed to consider the loads that have no side-effects. This patch fixed the issue by removing the unsafe loads from this function Eg: %vreg0<def> = L2_loadruh_io <fi#15>, 0 S2_storeri_io <fi#15>, 0, %vreg0 In this case, we load an unsigned extended half word and store this in to the same stack slot. The Stack slot coloring pass considers safe to remove the store. This patch marked all the non-vector byte and half word loads as unsafe. llvm-svn: 286843
* Timer: Remove group-less NamedRegionTimer constructor.Matthias Braun2016-11-101-2/+0
| | | | | | | | | | | | | | | The NamedRegionTimer initializer without a group name puts the Timer into the "Misc" group and is (nearly) unused. Remove it. The only user of this constructor appears to be the HexagonGenInsert pass, which creates a counter without group to count the complete execution time of that pass, however since every pass gets a counter by the PassManager anyway this should be unnecessary. Also removed the pointless TimerGroup there. Differential Revision: https://reviews.llvm.org/D25582 llvm-svn: 286524
* [Hexagon] Silence "sometimes uninitialized" warning in HexagonCopyToCombineKrzysztof Parzyszek2016-11-091-1/+3
| | | | llvm-svn: 286383
* [Hexagon] Separate Hexagon subreg indices for different register classesKrzysztof Parzyszek2016-11-0923-204/+255
| | | | | | | | | | | For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
* [Hexagon] Eliminate Insert4 pseudo-instruction, use combines insteadKrzysztof Parzyszek2016-11-093-48/+2
| | | | llvm-svn: 286368
* Reapply r286080 with a phony change in Hexagon's CMakeLists.txtKrzysztof Parzyszek2016-11-063-208/+107
| | | | | | | | Cmake has not recognized that Hexagon.td has a new dependency in HexagonPatterns.td. All changes to that file were not visible to the build bots. llvm-svn: 286084
* Revert r286080: it breaks build botsKrzysztof Parzyszek2016-11-062-97/+208
| | | | llvm-svn: 286081
* [Hexagon] Remove redundant custom selection codeKrzysztof Parzyszek2016-11-062-208/+97
| | | | | | | | | | | | | | | | The clr/set/toggle-bit instructions (with the bit index given as an immediate operand) had both, custom selection code that generated them, and selection patterns at the same time. The selection patterns were not used, because the custom selection code was executed first. This patch removes the custom code in favor of the selection patterns. The custom code handled 64-bit registers as well with an immediate bit index, and so new patterns were added to implement that. It was also the same case for the instruction "Rd += asr(Rs, Rt)", except that the custom code did not offer any additional functionality, and was simply removed. llvm-svn: 286080
* [Hexagon] Round 5 of selection pattern simplificationsKrzysztof Parzyszek2016-11-061-85/+53
| | | | | | Remove unnecessary type casts in patterns. llvm-svn: 286079
* [Hexagon] Round 4 of selection pattern simplificationsKrzysztof Parzyszek2016-11-062-101/+81
| | | | | | Give simpler or more meaningful names to pat frags and xforms. llvm-svn: 286078
* [Hexagon] Round 3 of selection pattern simplificationsKrzysztof Parzyszek2016-11-064-171/+76
| | | | | | | Remove unnecessary C++ functions for SDNode transforms. Move more pat frags to files where they are used. llvm-svn: 286077
* [Hexagon] Round 2 of selection pattern simplificationsKrzysztof Parzyszek2016-11-061-27/+29
| | | | | | Add pat frags for any-, sign-, and zero-extensions. llvm-svn: 286076
* [Hexagon] Relocate pattern-related bits to proper placesKrzysztof Parzyszek2016-11-056-57/+51
| | | | llvm-svn: 286049
* [Hexagon] Round 1 of selection pattern simplificationsKrzysztof Parzyszek2016-11-051-267/+267
| | | | | | | Consistently use register class pat frags instead of spelling out the type and class each time. llvm-svn: 286048
* [Hexagon] Split all selection patterns into a separate fileKrzysztof Parzyszek2016-11-058-3297/+3359
| | | | | | | This is just the basic separation, without any cleanup. Further changes will follow. llvm-svn: 286036
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