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* [Hexagon] Fix dependence check in the packetizerKrzysztof Parzyszek2017-06-013-189/+35
| | | | | | | An incorrect check in the packetizer lead to an attempt to convert an unconditional branch to a .new (conditional) form. llvm-svn: 304442
* [Hexagon] Handle long-running simplification loop in idiom recognitionKrzysztof Parzyszek2017-06-011-3/+5
| | | | | | | | | | | | | The initial assumption was that the simplification would converge to a fixed point relatvely quickly. Turns out that there are legitimate situa- tions where the complexity of the code causes it to take a large number of iterations. Two main changes: - Instead of aborting upon hitting the limit, simply return nullptr. - Reduce the limit to 10,000 from 100,000. llvm-svn: 304441
* TargetPassConfig: Keep a reference to an LLVMTargetMachine; NFCMatthias Braun2017-05-301-2/+2
| | | | | | | | | | | TargetPassConfig is not useful for targets that do not use the CodeGen library, so we may just as well store a pointer to an LLVMTargetMachine instead of just to a TargetMachine. While at it, also change the constructor to take a reference instead of a pointer as the TM must not be nullptr. llvm-svn: 304247
* [Hexagon] Improve code generation for 32x32-bit multiplicationKrzysztof Parzyszek2017-05-303-139/+115
| | | | | | | | | For multiplications of 64-bit values (giving 64-bit result), detect cases where the arguments are sign-extended 32-bit values, on a per- operand basis. This will allow few patterns to match a wider variety of combinations in which extensions can occur. llvm-svn: 304223
* [SelectionDAG] Set ISD::FPOWI to Expand by defaultCraig Topper2017-05-301-1/+1
| | | | | | | | | | | | | | | | | Summary: Currently FPOWI defaults to Legal and LegalizeDAG.cpp turns Legal into Expand for this opcode because Legal is a "lie". This patch changes the default for this opcode to Expand and removes the hack from LegalizeDAG.cpp. It also removes all the code in the targets that set this opcode to Expand themselves since they can just rely on the default. Reviewers: spatel, RKSimon, efriedma Reviewed By: RKSimon Subscribers: jfb, dschuff, sbc100, jgravelle-google, nemanjai, javed.absar, andrew.w.kaylor, llvm-commits Differential Revision: https://reviews.llvm.org/D33530 llvm-svn: 304215
* LivePhysRegs: Rework constructor + documentation; NFCMatthias Braun2017-05-262-3/+3
| | | | | | | - Take reference instead of pointer to a TRI that cannot be nullptr. - Improve documentation comments. llvm-svn: 304038
* [Hexagon] Cleanup of unused function isCalleeSaveReg (NFC)Sumanth Gundapaneni2017-05-262-6/+0
| | | | llvm-svn: 304034
* [Hexagon] Fix comment in HexagonPacketizer::runOnMachineFunctionKrzysztof Parzyszek2017-05-241-2/+2
| | | | | | | | Patch by Wei-Ren Chen. Differential Revision: https://reviews.llvm.org/D33439 llvm-svn: 303745
* [Hexagon] Fix definitions of vector predicate loads and storesKrzysztof Parzyszek2017-05-221-22/+17
| | | | | | This fixes http://llvm.org/PR33048. llvm-svn: 303572
* [IR] De-virtualize ~Value to save a vptrReid Kleckner2017-05-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Implements PR889 Removing the virtual table pointer from Value saves 1% of RSS when doing LTO of llc on Linux. The impact on time was positive, but too noisy to conclusively say that performance improved. Here is a link to the spreadsheet with the original data: https://docs.google.com/spreadsheets/d/1F4FHir0qYnV0MEp2sYYp_BuvnJgWlWPhWOwZ6LbW7W4/edit?usp=sharing This change makes it invalid to directly delete a Value, User, or Instruction pointer. Instead, such code can be rewritten to a null check and a call Value::deleteValue(). Value objects tend to have their lifetimes managed through iplist, so for the most part, this isn't a big deal. However, there are some places where LLVM deletes values, and those places had to be migrated to deleteValue. I have also created llvm::unique_value, which has a custom deleter, so it can be used in place of std::unique_ptr<Value>. I had to add the "DerivedUser" Deleter escape hatch for MemorySSA, which derives from User outside of lib/IR. Code in IR cannot include MemorySSA headers or call the MemoryAccess object destructors without introducing a circular dependency, so we need some level of indirection. Unfortunately, no class derived from User may have any virtual methods, because adding a virtual method would break User::getHungOffOperands(), which assumes that it can find the use list immediately prior to the User object. I've added a static_assert to the appropriate OperandTraits templates to help people avoid this trap. Reviewers: chandlerc, mehdi_amini, pete, dberlin, george.burgess.iv Reviewed By: chandlerc Subscribers: krytarowski, eraman, george.burgess.iv, mzolotukhin, Prazek, nlewycky, hans, inglorion, pcc, tejohnson, dberlin, llvm-commits Differential Revision: https://reviews.llvm.org/D31261 llvm-svn: 303362
* [LegacyPassManager] Remove TargetMachine constructorsFrancis Visoiu Mistrih2017-05-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This provides a new way to access the TargetMachine through TargetPassConfig, as a dependency. The patterns replaced here are: * Passes handling a null TargetMachine call `getAnalysisIfAvailable<TargetPassConfig>`. * Passes not handling a null TargetMachine `addRequired<TargetPassConfig>` and call `getAnalysis<TargetPassConfig>`. * MachineFunctionPasses now use MF.getTarget(). * Remove all the TargetMachine constructors. * Remove INITIALIZE_TM_PASS. This fixes a crash when running `llc -start-before prologepilog`. PEI needs StackProtector, which gets constructed without a TargetMachine by the pass manager. The StackProtector pass doesn't handle the case where there is no TargetMachine, so it segfaults. Related to PR30324. Differential Revision: https://reviews.llvm.org/D33222 llvm-svn: 303360
* [KnownBits] Add bit counting methods to KnownBits struct and use them where ↵Craig Topper2017-05-121-1/+1
| | | | | | | | | | | | possible This patch adds min/max population count, leading/trailing zero/one bit counting methods. The min methods return answers based on bits that are known without considering unknown bits. The max methods give answers taking into account the largest count that unknown bits could give. Differential Revision: https://reviews.llvm.org/D32931 llvm-svn: 302925
* Add extra operand to CALLSEQ_START to keep frame part set up previouslySerge Pavlov2017-05-093-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 llvm-svn: 302527
* [Hexagon] Disable predicated calls by defaultKrzysztof Parzyszek2017-05-053-1/+18
| | | | llvm-svn: 302307
* [Hexagon] Remove C6 and C7 as separate registersKrzysztof Parzyszek2017-05-053-20/+6
| | | | | | | These are M0 and M1. Removing duplicated registers reduces the number of explicit register aliasing. llvm-svn: 302306
* [RDF] Remove covered parts of reached uses for phi and use in same blockKrzysztof Parzyszek2017-05-053-13/+36
| | | | llvm-svn: 302305
* [Hexagon] Use automatically-generated scheduling information for HVXKrzysztof Parzyszek2017-05-0327-8023/+9998
| | | | | | Patch by Jyotsna Verma. llvm-svn: 302073
* [Hexagon] Handle S2_storerf_io in HexagonInstrInfoKrzysztof Parzyszek2017-05-031-0/+1
| | | | llvm-svn: 302036
* [Hexagon] Misc fixes in HexagonInstrInfo, NFCKrzysztof Parzyszek2017-05-031-15/+2
| | | | | | Formatting changes + remove unused function. llvm-svn: 302035
* [Hexagon] Adjust latency between allocframe and the first store on stackKrzysztof Parzyszek2017-05-031-0/+5
| | | | | | | | | | | | Allocframe and the following stores on the stack have a latency of 2 cycles when not in the same packet. This happens because R29 is needed early by the store instruction. Since one of such stores can be packetized along with allocframe and use old value of R29, we can assign it 0 cycle latency while leaving latency of other stores to the default value of 2 cycles. Patch by Jyotsna Verma. llvm-svn: 302034
* [Hexagon] Handle J2_jumptpt and J2_jumpfpt in HexagonInstrInfoKrzysztof Parzyszek2017-05-031-8/+25
| | | | llvm-svn: 302033
* [Hexagon] Implement undoing .cur instructions in packetizerKrzysztof Parzyszek2017-05-033-2/+25
| | | | | | | | | | | | | The packetizer needs to convert .cur instruction to its regular form if the use is not in the same packet as the .cur. The code in the packetizer handles one type of .cur, which is the vector load case. This patch updates the packetizer so that it can undo all the .cur instructions. In the test case, the .cur is the 128B version, but there are also the post-increment versions. Patch by Brendon Cahoon. llvm-svn: 302032
* [Hexagon] Add memory operands to a rewritten loadKrzysztof Parzyszek2017-05-031-2/+3
| | | | llvm-svn: 302030
* [Hexagon] Reset spill alignment when variable-sized objects are presentKrzysztof Parzyszek2017-05-031-0/+30
| | | | llvm-svn: 302029
* [Hexagon] Fix uninitialized value caught with valgrindKrzysztof Parzyszek2017-05-021-1/+1
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301957
* [Hexagon] Change iconst to emit 27bit relocationKrzysztof Parzyszek2017-05-0212-25/+32
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301956
* [Hexagon] Add extenders for GD_PLT_B22_PCREL and LD_PLT_B22_PCRELKrzysztof Parzyszek2017-05-026-5/+49
| | | | | | Patch by Sid Manning. llvm-svn: 301955
* [Hexagon] Don't ignore mult-cycle latency informationKrzysztof Parzyszek2017-05-023-15/+30
| | | | | | | | | | | | | | | | | | | | | | | | The compiler was generating code that ends up ignoring a multiple latency dependence between two instructions by scheduling the intructions in back-to-back packets. The packetizer needs to end a packet if the latency of the current current insruction and the source in the previous packet is greater than 1 cycle. This case occurs when there is still room in the current packet, but scheduling the instruction causes a stall. Instead, the packetizer should start a new packet. Also, if the current packet already contains a stall, then it is okay to add another instruction to the packet that also causes a stall. This occurs when there are no instructions that can be scheduled in between the producer and consumer instructions. This patch changes the latency for loads to 2 cycles from 3 cycles. This change refects that a load only needs to be separated by one extra packet to eliminate the stall. Patch by Ikhlas Ajbar. llvm-svn: 301954
* [Hexagon] Formatting changes, NFCKrzysztof Parzyszek2017-05-024-8/+13
| | | | llvm-svn: 301953
* [Hexagon] Remove unused validSubtarget TSFlagsKrzysztof Parzyszek2017-05-028-58/+4
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301952
* [Hexagon] Make sure duplexed dealloc_returns are checked for double jumpsKrzysztof Parzyszek2017-05-021-0/+8
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301951
* [Hexagon] Move checking AXOK to checkerKrzysztof Parzyszek2017-05-023-69/+80
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301949
* [Hexagon] Remove unneeded code from HexagonShufflerKrzysztof Parzyszek2017-05-022-11/+9
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301947
* [Hexagon] Extract function that checks endloops with other branchesKrzysztof Parzyszek2017-05-022-36/+39
| | | | | | | | Change location number to point to conflicting branch instruction. Patch by Colin LeMahieu. llvm-svn: 301946
* [Hexagon] Add new packet iterator which will iterate through duplexesKrzysztof Parzyszek2017-05-023-24/+82
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301945
* [Hexagon] Check for .cur def without use without using a map data structureKrzysztof Parzyszek2017-05-022-24/+42
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301943
* [Hexagon] Replace CVI_VM_CUR_LD type with CVI_VM_LDKrzysztof Parzyszek2017-05-0110-114/+187
| | | | | | | | A .cur instruction can be identified by checking isCVINew() && mayLoad(). Patch by Colin LeMahieu. llvm-svn: 301829
* [Hexagon] Improving error reporting for writing to read only registersKrzysztof Parzyszek2017-05-013-8/+23
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301828
* [Hexagon] Give better error messages for solo instruction errorsKrzysztof Parzyszek2017-05-012-7/+11
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301827
* [Hexagon] Improve shuffle error reportingKrzysztof Parzyszek2017-05-0111-482/+276
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301823
* [RDF] Correctly calculate lane masks for defsKrzysztof Parzyszek2017-04-281-2/+7
| | | | llvm-svn: 301700
* [Hexagon] Do not move a block if it is on a fall-through pathKrzysztof Parzyszek2017-04-281-3/+10
| | | | llvm-svn: 301698
* Kill off the old SimplifyInstruction API by converting remaining users.Daniel Berlin2017-04-281-3/+3
| | | | llvm-svn: 301673
* Use Argument::hasAttribute and AttributeList::ReturnIndex moreReid Kleckner2017-04-281-6/+3
| | | | | | | | | | | This eliminates many extra 'Idx' induction variables in loops over arguments in CodeGen/ and Target/. It also reduces the number of places where we assume that ReturnIndex is 0 and that we should add one to argument numbers to get the corresponding attribute list index. NFC llvm-svn: 301666
* Fix typo and place comment close to its targetKrzysztof Parzyszek2017-04-271-5/+6
| | | | | | | | Patch by Wei-Ren Chen. Differential Revision: https://reviews.llvm.org/D32594 llvm-svn: 301546
* [ValueTracking] Introduce a KnownBits struct to wrap the two APInts for ↵Craig Topper2017-04-261-4/+4
| | | | | | | | | | | | | | | | computeKnownBits This patch introduces a new KnownBits struct that wraps the two APInt used by computeKnownBits. This allows us to treat them as more of a unit. Initially I've just altered the signatures of computeKnownBits and InstCombine's simplifyDemandedBits to pass a KnownBits reference instead of two separate APInt references. I'll do similar to the SelectionDAG version of computeKnownBits/simplifyDemandedBits as a separate patch. I've added a constructor that allows initializing both APInts to the same bit width with a starting value of 0. This reduces the repeated pattern of initializing both APInts. Once place default constructed the APInts so I added a default constructor for those cases. Going forward I would like to add more methods that will work on the pairs. For example trunc, zext, and sext occur on both APInts together in several places. We should probably add a clear method that can be used to clear both pieces. Maybe a method to check for conflicting information. A method to return (Zero|One) so we don't write it out everywhere. Maybe a method for (Zero|One).isAllOnesValue() to determine if all bits are known. I'm sure there are many other methods we can come up with. Differential Revision: https://reviews.llvm.org/D32376 llvm-svn: 301432
* [Hexagon] Only increment debug counters if debug option is presentKrzysztof Parzyszek2017-04-251-6/+11
| | | | llvm-svn: 301346
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-245-34/+36
| | | | | | | | | | | | | | | 1. RegisterClass::getSize() is split into two functions: - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const; - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const; 2. RegisterClass::getAlignment() is replaced by: - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const; This will allow making those values depend on subtarget features in the future. Differential Revision: https://reviews.llvm.org/D31783 llvm-svn: 301221
* Revert "[APInt] Fix a few places that use APInt::getRawData to operate ↵Renato Golin2017-04-231-1/+1
| | | | | | | | | | | | | | | | within the normal API." This reverts commit r301105, 4, 3 and 1, as a follow up of the previous revert, which broke even more bots. For reference: Revert "[APInt] Use operator<<= where possible. NFC" Revert "[APInt] Use operator<<= instead of shl where possible. NFC" Revert "[APInt] Use ashInPlace where possible." PR32754. llvm-svn: 301111
* [APInt] Fix a few places that use APInt::getRawData to operate within the ↵Craig Topper2017-04-231-1/+1
| | | | | | | | | | normal API. getRawData exposes the internal type of the APInt class directly to its users. Ideally we wouldn't expose such an implementation detail. This patch fixes a few of the easy cases by using truncate, extract, or a rotate. llvm-svn: 301105
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