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* [Hexagon] Remove vectors of i64 from valid HVX typesKrzysztof Parzyszek2017-12-145-69/+24
| | | | | | HVX does not support operations on 64-bit integers. llvm-svn: 320722
* [Targets] Don't automatically include the scheduler class enum from ↵Craig Topper2017-12-131-0/+1
| | | | | | | | | | *GenInstrInfo.inc with GET_INSTRINFO_ENUM. Make targets request is separately. Most of the targets don't need the scheduler class enum. I have an X86 scheduler model change that causes some names in the enum to become about 18000 characters long. This is because using instregex in scheduler models causes the scheduler class to get named with every instruction that matches the regex concatenated together. MSVC has a limit of 4096 characters for an identifier name. Rather than trying to come up with way to reduce the name length, I'm just going to sidestep the problem by not including the enum in X86. llvm-svn: 320552
* Rename LiveIntervalAnalysis.h to LiveIntervals.hMatthias Braun2017-12-133-1/+3
| | | | | | | | | | Headers/Implementation files should be named after the class they declare/define. Also eliminated an `#include "llvm/CodeGen/LiveIntervalAnalysis.h"` in favor of `class LiveIntarvals;` llvm-svn: 320546
* [Hexagon] Better detection of identity and undef masks in shufflesKrzysztof Parzyszek2017-12-121-3/+17
| | | | llvm-svn: 320523
* [Hexagon] Fix wrong order of operands for vmuxKrzysztof Parzyszek2017-12-121-1/+1
| | | | | | | | | | | | Shuffle generation uses vmux to collapse vectors resulting from two individual shuffles into one. The indexes of the elements selected from the first operand were indicated by 0xFF in the constant vector used in the compare instruction, but the compare (veqb) set the bits corresponding to the 0x00 elements, thus inverting the selection. Reverse the order of operands to vmux to get the correct output. llvm-svn: 320516
* [Hexagon] Add support for Hexagon V65Krzysztof Parzyszek2017-12-1152-5590/+11596
| | | | llvm-svn: 320404
* [Hexagon] Crash in instruction selection for insert_vector_elt for HVXKrzysztof Parzyszek2017-12-111-1/+1
| | | | | | | | A wrong type was passed to insertVector, causing an out-of-bounds value to be added an an operand to HexagonISD::INSERT. This later failed in instruction selection. llvm-svn: 320369
* [RISCV] Support lowering FrameIndexAlex Bradbury2017-12-112-21/+0
| | | | | | | | | | | | | | | | Introduces the AddrFI "addressing mode", which is necessary simply because it's not possible to write a pattern that directly matches a frameindex. Ensure callee-saved registers are accessed relative to the stackpointer. This is necessary as callee-saved register spills are performed before the frame pointer is set. Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can make use of it in the RISC-V backend. Differential Revision: https://reviews.llvm.org/D39848 llvm-svn: 320353
* Fix 'enumeral and non-enumeral type in conditional expression' gcc warning. ↵Simon Pilgrim2017-12-091-1/+1
| | | | | | NFCI. llvm-svn: 320254
* Fix signed/unsigned gcc warning. NFCI.Simon Pilgrim2017-12-091-1/+1
| | | | llvm-svn: 320253
* [ModRefInfo] Make enum ModRefInfo an enum class [NFC].Alina Sbirlea2017-12-071-5/+5
| | | | | | | | | | | | | | | Summary: Make enum ModRefInfo an enum class. Changes to ModRefInfo values should be done using inline wrappers. This should prevent future bit-wise opearations from being added, which can be more error-prone. Reviewers: sanjoy, dberlin, hfinkel, george.burgess.iv Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40933 llvm-svn: 320107
* [Hexagon] Generate HVX code for basic arithmetic operationsKrzysztof Parzyszek2017-12-074-30/+137
| | | | | | Handle and, or, xor, add, sub, mul for vectors of i8, i16, and i32. llvm-svn: 320063
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-0713-78/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. For MachineOperand::print, keep a simple version that can be easily called from `dump()`, and a more complex one which will be called from both the MIRPrinter and MachineInstr::print. Add extra checks inside MachineOperand for detached operands (operands with getParent() == nullptr). https://reviews.llvm.org/D40836 * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+)<def> ([^ ]+)/kill: \1 def \2 \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: def ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: def \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/<def>//g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<kill>/killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use,kill>/implicit killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<def[ ]*,[ ]*dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def[ ]*,[ ]*dead>/implicit-def dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def>/implicit-def \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use>/implicit \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<internal>/internal \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<undef>/undef \1/g' llvm-svn: 320022
* [Hexagon] Recognize vdealb, vdealh, vshuffb and vshuffh specificallyKrzysztof Parzyszek2017-12-061-4/+37
| | | | llvm-svn: 319978
* [Hexagon] Handle perfect shuffles on single vectorsKrzysztof Parzyszek2017-12-061-6/+19
| | | | llvm-svn: 319965
* [ModRefInfo] Do not use ModRefInfo result in if conditions as this makesAlina Sbirlea2017-12-061-1/+2
| | | | | | | assumptions about the values in the enum. Replace with wrapper returning bool [NFC]. llvm-svn: 319949
* [Hexagon] Suppress more warnings on unused variables defined for asserts.Tim Shen2017-12-061-0/+1
| | | | llvm-svn: 319944
* [Hexagon] Suppress warnings on unused variables defind for asserts.Tim Shen2017-12-061-0/+2
| | | | llvm-svn: 319940
* [Target] dumpr() is defined only in debug builds.Davide Italiano2017-12-061-0/+2
| | | | | | This fixes the clang build on macOS. llvm-svn: 319923
* [Hexagon] Generate HVX code for vector construction and accessKrzysztof Parzyszek2017-12-068-248/+2468
| | | | | | | | | | Support for: - build vector, - extract vector element, subvector, - insert vector element, subvector, - shuffle. llvm-svn: 319901
* Modify ModRefInfo values using static inline method abstractions [NFC].Alina Sbirlea2017-12-051-1/+2
| | | | | | | | | | | | | | | | | Summary: The aim is to make ModRefInfo checks and changes more intuitive and less error prone using inline methods that abstract the bit operations. Ideally ModRefInfo would become an enum class, but that change will require a wider set of changes into FunctionModRefBehavior. Reviewers: sanjoy, george.burgess.iv, dberlin, hfinkel Subscribers: nlopes, llvm-commits Differential Revision: https://reviews.llvm.org/D40749 llvm-svn: 319821
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-0416-85/+89
| | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
* [Hexagon] Implement HexagonSubtarget::useAA()Krzysztof Parzyszek2017-11-302-1/+14
| | | | llvm-svn: 319477
* [Hexagon] Solo instructions cannot be used with new value jumpsKrzysztof Parzyszek2017-11-301-0/+3
| | | | llvm-svn: 319470
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-3011-107/+107
| | | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
* [Hexagon] Remove HexagonISD::PACKHLKrzysztof Parzyszek2017-11-293-6/+1
| | | | llvm-svn: 319352
* [Hexagon] Create helpers extractVector and insertVector in loweringKrzysztof Parzyszek2017-11-292-139/+144
| | | | llvm-svn: 319351
* [Hexagon] Use stable sort for HexagonShuffler to remove non-deterministic ↵Mandeep Singh Grang2017-11-281-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ordering Summary: This fixes failures in the following tests uncovered by D39245: LLVM :: CodeGen/Hexagon/args.ll LLVM :: CodeGen/Hexagon/constp-extract.ll LLVM :: CodeGen/Hexagon/expand-condsets-basic.ll LLVM :: CodeGen/Hexagon/gp-rel.ll LLVM :: CodeGen/Hexagon/packetize_cond_inst.ll LLVM :: CodeGen/Hexagon/simple_addend.ll LLVM :: CodeGen/Hexagon/swp-stages4.ll LLVM :: CodeGen/Hexagon/swp-vmult.ll LLVM :: CodeGen/Hexagon/swp-vsum.ll LLVM :: MC/Hexagon/align.s LLVM :: MC/Hexagon/asmMap.s LLVM :: MC/Hexagon/dis-duplex-p0.s LLVM :: MC/Hexagon/double-vector-producer.s LLVM :: MC/Hexagon/inst_select.ll LLVM :: MC/Hexagon/instructions/j.s Reviewers: colinl, kparzysz, adasgupt, slarin Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40227 llvm-svn: 319223
* [Hexagon] Make sure to zero-extend bytes before building a vectorKrzysztof Parzyszek2017-11-281-10/+12
| | | | llvm-svn: 319204
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-2812-53/+53
| | | | | | | | | | | As part of the unification of the debug format and the MIR format, always print registers as lowercase. * Only debug printing is affected. It now follows MIR. Differential Revision: https://reviews.llvm.org/D40417 llvm-svn: 319187
* Use getStoreSize() in various places instead of 'BitSize >> 3'.Jonas Paulsson2017-11-281-10/+2
| | | | | | | | | | | | | | | | | | This is needed for cases when the memory access is not as big as the width of the data type. For instance, storing i1 (1 bit) would be done in a byte (8 bits). Using 'BitSize >> 3' (or '/ 8') would e.g. give the memory access of an i1 a size of 0, which for instance makes alias analysis return NoAlias even when it shouldn't. There are no tests as this was done as a follow-up to the bugfix for the case where this was discovered (r318824). This handles more similar cases. Review: Björn Petterson https://reviews.llvm.org/D40339 llvm-svn: 319173
* [CodeGen] Rename functions PrintReg* to printReg*Francis Visoiu Mistrih2017-11-2816-55/+55
| | | | | | | | | | | LLVM Coding Standards: Function names should be verb phrases (as they represent actions), and command-like function should be imperative. The name should be camel case, and start with a lower case letter (e.g. openFile() or isFoo()). Differential Revision: https://reviews.llvm.org/D40416 llvm-svn: 319168
* [Hexagon] Implement HexagonSubtarget::isHVXVectorTypeKrzysztof Parzyszek2017-11-272-27/+14
| | | | llvm-svn: 319064
* [Hexagon] Implement buildVector32 and buildVector64 as utility functionsKrzysztof Parzyszek2017-11-222-133/+146
| | | | | | | | | Change LowerBUILD_VECTOR to use those functions. This commit will tempora- rily affect constant vector generation (it will generate constant-extended values instead of non-extended combines), but the code for the general case should be better. The constant selection part will be fixed later. llvm-svn: 318877
* [Hexagon] Add patterns to select A2_combine_ll and its variantsKrzysztof Parzyszek2017-11-221-0/+10
| | | | llvm-svn: 318876
* [Hexagon] Remove trailing spaces, NFCKrzysztof Parzyszek2017-11-222-3/+3
| | | | llvm-svn: 318875
* [Hexagon] Add HexagonSubtarget::getVectorLength()Krzysztof Parzyszek2017-11-211-0/+9
| | | | llvm-svn: 318807
* [Hexagon] Make sure that RDF does not remove EH_LABELsKrzysztof Parzyszek2017-11-211-1/+2
| | | | | | | Since EH_LABELs (and other labels) no longer have "side-effects", they should be checked for separately. llvm-svn: 318801
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-1734-48/+48
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* Add NDEBUG checks around LLVM_DUMP_METHOD functions for Wunused-function ↵Eric Christopher2017-11-161-1/+3
| | | | | | warnings. llvm-svn: 318373
* Add backend name to Target to enable runtime info to be fed back into TableGenDaniel Sanders2017-11-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | Summary: Make it possible to feed runtime information back to tablegen to enable profile-guided tablegen-eration, detection of untested tablegen definitions, etc. Being a cross-compiler by nature, LLVM will potentially collect data for multiple architectures (e.g. when running 'ninja check'). We therefore need a way for TableGen to figure out what data applies to the backend it is generating at the time. This patch achieves that by including the name of the 'def X : Target ...' for the backend in the TargetRegistry. Reviewers: qcolombet Reviewed By: qcolombet Subscribers: jholewinski, arsenm, jyknight, aditya_nandakumar, sdardis, nemanjai, ab, nhaehnle, t.p.northover, javed.absar, qcolombet, llvm-commits, fedor.sergeev Differential Revision: https://reviews.llvm.org/D39742 llvm-svn: 318352
* Recommit r317904: [Hexagon] Create HexagonISelDAGToDAG.h, NFCKrzysztof Parzyszek2017-11-102-109/+139
| | | | | | | The Windows builder did not reconstruct the HexagonGenDAGISel.inc file after the TableGen binary has changed. llvm-svn: 317921
* Revert "[Hexagon] Create HexagonISelDAGToDAG.h, NFC"Krzysztof Parzyszek2017-11-102-139/+109
| | | | | | This reverts r317904: broke Windows build. llvm-svn: 317916
* [Hexagon] Create HexagonISelDAGToDAG.h, NFCKrzysztof Parzyszek2017-11-102-109/+139
| | | | llvm-svn: 317904
* Set hasSideEffects=0 for PHI and fix affected passesAlex Bradbury2017-11-081-3/+2
| | | | | | | | | | | | | | Previously, hasSideEffects was ? for TargetOpcode::PHI and would be inferred as 1. D37065 sets the previously inferred properties explicitly. This patch sets hasSideEffects=0 for PHI, as it is for G_PHI. MachineInstr::isSafeToMove has been updated so it still returns false for PHI. Additionally, HexagonBitSimplify relied on a PHI node having the hasUnmodeledSideEffects property. This patch fixes that assumption. Differential Revision: https://reviews.llvm.org/D37097 llvm-svn: 317721
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-0810-10/+10
| | | | | | | | This header includes CodeGen headers, and is not, itself, included by any Target headers, so move it into CodeGen to match the layering of its implementation. llvm-svn: 317647
* [Hexagon] Make a test more flexible in HexagonLoopIdiomRecognitionKrzysztof Parzyszek2017-11-071-18/+51
| | | | | | | | | An "or" that sets the sign-bit can be replaced with a "xor", if the sign-bit was known to be clear before. With some changes to instruction combining, the simple sign-bit check was failing. Replace it with a more flexible one to catch more cases. llvm-svn: 317592
* Move TargetFrameLowering.h to CodeGen where it's implementedDavid Blaikie2017-11-031-1/+1
| | | | | | | | | | | This header already includes a CodeGen header and is implemented in lib/CodeGen, so move the header there to match. This fixes a link error with modular codegeneration builds - where a header and its implementation are circularly dependent and so need to be in the same library, not split between two like this. llvm-svn: 317379
* Add llvm::for_each as a range-based extensions to <algorithm> and make use ↵Aaron Ballman2017-11-031-8/+7
| | | | | | of it in some cases where it is a more clear alternative to std::for_each. llvm-svn: 317356
* [Hexagon] Prefer L2_loadrub_io over L4_loadrub_rrKrzysztof Parzyszek2017-11-021-52/+82
| | | | | | | If the offset is an immediate, avoid putting it in a register to get Rs+Rt<<#0. llvm-svn: 317275
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