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* [Hexagon] Add patterns for sext_inreg of HVX vector typesKrzysztof Parzyszek2018-01-231-0/+19
| | | | llvm-svn: 323250
* [Hexagon] Implement hasLoadFromStackSlot and hasStoreToStackSlotKrzysztof Parzyszek2018-01-232-0/+50
| | | | | | | | If the instruction is a bundle, check the instructions inside of it. Patch by Suyog Sarda. llvm-svn: 323240
* [Hexagon] Fix unused variable warning in release buildKrzysztof Parzyszek2018-01-231-0/+1
| | | | llvm-svn: 323233
* [Hexagon] Implement basic vector operations on vectors vNi1Krzysztof Parzyszek2018-01-238-260/+970
| | | | | | | | | | | In addition to that, make sure that there are no boolean vector types that are associated with multiple register classes. Specifically, remove v32i1 and v64i1 from integer register classes. These types will correspond to results of vector comparisons, and as such should belong to the vector predicate class. Having them in scalar registers as well makes legalization ambiguous. llvm-svn: 323229
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-01-222-3/+3
| | | | | | "the the" -> "the" llvm-svn: 323074
* [Hexagon] Implement signed and unsigned multiply-high for vectorsKrzysztof Parzyszek2018-01-154-3/+166
| | | | llvm-svn: 322499
* [Hexagon] Rewrite LowerVECTOR_SHUFFLE for 32-/64-bit vectorsKrzysztof Parzyszek2018-01-151-38/+115
| | | | | | | The old implementation was not always correct. The new one recognizes more shuffles that match specific instructions. llvm-svn: 322498
* Silence GCC 7 warning by using an enum class.Florian Hahn2018-01-121-36/+42
| | | | | | | | | | | | | | | | | This silences the following GCC7 warning: lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp:142:30: warning: enumeral and non-enumeral type in conditional expression [-Wextra] return F != Colors.end() ? F->second : None; ~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~ Reviewers: amharc, RKSimon, davide Reviewed By: RKSimon, davide Differential Revision: https://reviews.llvm.org/D41003 llvm-svn: 322398
* MC: Remove redundant `SetUsed` arguments in MCSymbol methodsSam Clegg2018-01-121-1/+1
| | | | | | | | | | | We can probably take this a step further since the only user of the isUsed flag is AsmParser it should probably be doing this explicitly. For now this is a step in the right direction though. Differential Revision: https://reviews.llvm.org/D41971 llvm-svn: 322386
* [Hexagon] Fix building 64-bit vector from constant valuesKrzysztof Parzyszek2018-01-111-1/+1
| | | | | | The constants were aggregated in a reverse order. llvm-svn: 322303
* [Hexagon] Cast elements to correct type when creating constant vectorKrzysztof Parzyszek2018-01-111-1/+2
| | | | llvm-svn: 322301
* [Hexagon] Impose limits on container sizes in HexagonGenInsertKrzysztof Parzyszek2018-01-111-3/+20
| | | | | | | With over 300k virtual registers, the size of the data exceeded 12GB. Impose limits on how much information is collected. llvm-svn: 322299
* [Hexagon] Use SetVector when queuing nodes to scan in selectVectorConstantsKrzysztof Parzyszek2018-01-111-3/+4
| | | | llvm-svn: 322298
* Remove unused function HvxSelector::zerous.Eric Christopher2018-01-091-20/+0
| | | | llvm-svn: 322053
* [Hexagon] Even simpler patterns for sign- and zero-extending HVX vectorsKrzysztof Parzyszek2018-01-051-16/+4
| | | | | | Recommit r321897 with updated testcases. llvm-svn: 321908
* Revert r321894: it requires a part of another commit that is not ready yetKrzysztof Parzyszek2018-01-051-19/+0
| | | | | | | Commit message: [Hexagon] Add patterns for sext_inreg of HVX vector types llvm-svn: 321904
* Revert r321897: affected testcases were not updatedKrzysztof Parzyszek2018-01-051-4/+16
| | | | | | | Commit message: [Hexagon] Even simpler patterns for sign- and zero-extending HVX vectors llvm-svn: 321902
* [Hexagon] Even simpler patterns for sign- and zero-extending HVX vectorsKrzysztof Parzyszek2018-01-051-16/+4
| | | | llvm-svn: 321897
* [Hexagon] Add patterns for truncating HVX vector typesKrzysztof Parzyszek2018-01-051-0/+5
| | | | | | Only non-bool vectors. llvm-svn: 321895
* [Hexagon] Add patterns for sext_inreg of HVX vector typesKrzysztof Parzyszek2018-01-051-0/+19
| | | | llvm-svn: 321894
* [Hexagon] Add a bitcast to required type in LowerHvxMulKrzysztof Parzyszek2018-01-051-1/+2
| | | | llvm-svn: 321893
* [Hexagon] Add pattern for vsplat to v8i8Krzysztof Parzyszek2018-01-051-0/+5
| | | | llvm-svn: 321892
* [Hexagon] Set boolean contents in HexagonISelLoweringKrzysztof Parzyszek2018-01-051-0/+2
| | | | llvm-svn: 321891
* [Hexagon] Replace INSERTRP/EXTRACTRP with INSERT/EXTRACT in HexagonISDKrzysztof Parzyszek2018-01-043-41/+25
| | | | llvm-svn: 321798
* Thread MCSubtargetInfo through Target::createMCAsmBackendAlex Bradbury2018-01-032-5/+6
| | | | | | | | | | | | | | | | | | | | | Currently it's not possible to access MCSubtargetInfo from a TgtMCAsmBackend. D20830 threaded an MCSubtargetInfo reference through MCAsmBackend::relaxInstruction, but this isn't the only function that would benefit from access. This patch removes the Triple and CPUString arguments from createMCAsmBackend and replaces them with MCSubtargetInfo. This patch just changes the interface without making any intentional functional changes. Once in, several cleanups are possible: * Get rid of the awkward MCSubtargetInfo handling in ARMAsmBackend * Support 16-bit instructions when valid in MipsAsmBackend::writeNopData * Get rid of the CPU string parsing in X86AsmBackend and just use a SubtargetFeature for HasNopl * Emit 16-bit nops in RISCVAsmBackend::writeNopData if the compressed instruction set extension is enabled (see D41221) This change initially exposed PR35686, which has since been resolved in r321026. Differential Revision: https://reviews.llvm.org/D41349 llvm-svn: 321692
* [Hexagon] Fix generation of vector sign extensionsKrzysztof Parzyszek2018-01-021-17/+27
| | | | llvm-svn: 321650
* Use phi ranges to simplify code. No functionality change intended.Benjamin Kramer2017-12-301-7/+4
| | | | llvm-svn: 321585
* Make helpers static. No functionality change.Benjamin Kramer2017-12-241-1/+9
| | | | llvm-svn: 321425
* (Re-landing) Expose a TargetMachine::getTargetTransformInfo functionSanjoy Das2017-12-222-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Re-land r321234. It had to be reverted because it broke the shared library build. The shared library build broke because there was a missing LLVMBuild dependency from lib/Passes (which calls TargetMachine::getTargetIRAnalysis) to lib/Target. As far as I can tell, this problem was always there but was somehow masked before (perhaps because TargetMachine::getTargetIRAnalysis was a virtual function). Original commit message: This makes the TargetMachine interface a bit simpler. We still need the std::function in TargetIRAnalysis to avoid having to add a dependency from Analysis to Target. See discussion: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119749.html I avoided adding all of the backend owners to this review since the change is simple, but let me know if you feel differently about this. Reviewers: echristo, MatzeB, hfinkel Reviewed By: hfinkel Subscribers: jholewinski, jfb, arsenm, dschuff, mcrosier, sdardis, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, llvm-commits Differential Revision: https://reviews.llvm.org/D41464 llvm-svn: 321375
* Revert "Expose a TargetMachine::getTargetTransformInfo function"Sanjoy Das2017-12-212-4/+5
| | | | | | This reverts commit r321234. It breaks the -DBUILD_SHARED_LIBS=ON build. llvm-svn: 321243
* Expose a TargetMachine::getTargetTransformInfo functionSanjoy Das2017-12-212-5/+4
| | | | | | | | | | | | | | | | | | | | | | | Summary: This makes the TargetMachine interface a bit simpler. We still need the std::function in TargetIRAnalysis to avoid having to add a dependency from Analysis to Target. See discussion: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119749.html I avoided adding all of the backend owners to this review since the change is simple, but let me know if you feel differently about this. Reviewers: echristo, MatzeB, hfinkel Reviewed By: hfinkel Subscribers: jholewinski, jfb, arsenm, dschuff, mcrosier, sdardis, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, llvm-commits Differential Revision: https://reviews.llvm.org/D41464 llvm-svn: 321234
* Attempt to pacify 4.8.5 with makeArrayRefReid Kleckner2017-12-211-1/+1
| | | | llvm-svn: 321233
* [Hexagon] Use ArrayRef member functions instead of custom onesKrzysztof Parzyszek2017-12-201-19/+10
| | | | llvm-svn: 321221
* [Hexagon] Allow construction of HVX vector predicatesKrzysztof Parzyszek2017-12-206-161/+363
| | | | | | Handle BUILD_VECTOR of boolean values. llvm-svn: 321220
* [Hexagon] Legalize vector elements to i32 in buildVector32/64Krzysztof Parzyszek2017-12-201-15/+22
| | | | llvm-svn: 321218
* [Hexagon] Adjust the value type for BCvt in LowerFormalArgumentsKrzysztof Parzyszek2017-12-201-2/+8
| | | | llvm-svn: 321177
* [Hexagon] Cache loads to select to avoid traversing mutating DAGKrzysztof Parzyszek2017-12-181-12/+29
| | | | llvm-svn: 321034
* Fix inconsistent line endings in HexagonVectorLoopCarriedReuse.cpp. NFC.Dimitry Andric2017-12-181-7/+7
| | | | llvm-svn: 321009
* [Hexagon] Higher versions of HVX imply presence of lower versionsKrzysztof Parzyszek2017-12-181-6/+6
| | | | | | | The code in Hexagon_MC::completeHVXFeatures wasn't setting all HVX- related features correctly. llvm-svn: 321008
* i[Hexagon] ANY_EXTEND_VECTOR_INREG should be Custom, not Legal in r321004Krzysztof Parzyszek2017-12-181-1/+2
| | | | llvm-svn: 321005
* [Hexagon] Generate HVX code for vector sign-, zero- and any-extendsKrzysztof Parzyszek2017-12-184-0/+38
| | | | | | Implement any-extend as zero-extend. llvm-svn: 321004
* [Hexagon] Prefer to widen HVX vectors instead of promotingKrzysztof Parzyszek2017-12-182-0/+14
| | | | llvm-svn: 321002
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-1525-48/+45
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* [Hexagon] Remove recursion in visitUsesOf, replace with use queueKrzysztof Parzyszek2017-12-152-43/+121
| | | | | | | | | | | | | | | | This is primarily to reduce stack usage, but ordering the use queue according to the position in the code (earlier instructions visited before later ones) reduces the number of unnecessary bottoms due to visiting instructions out of order, e.g. %reg1 = copy %reg0 %reg2 = copy %reg0 %reg3 = and %reg1, %reg2 Here, reg3 should be known to be same as reg0-2, but if reg3 is evaluated after reg1 is updated, but before reg2 is updated, the two inputs to the and will appear different, causing reg3 to become bottom. llvm-svn: 320866
* [Hexagon] Handle concat_vectors of all allowed HVX typesKrzysztof Parzyszek2017-12-151-10/+17
| | | | llvm-svn: 320865
* [Hexagon] Fix operand-swapping PatFrag for atomic storesKrzysztof Parzyszek2017-12-151-18/+22
| | | | | | | PatFrag now has the atomicity information stored as bit fields. They need to be copied to the new PatFrag. llvm-svn: 320855
* Remove a non-modular header (& inline it into its one use)David Blaikie2017-12-142-68/+55
| | | | llvm-svn: 320768
* TLI: Allow using PSV for intrinsic mem operandsMatt Arsenault2017-12-142-0/+2
| | | | llvm-svn: 320756
* DAG: Expose all MMO flags in getTgtMemIntrinsicMatt Arsenault2017-12-141-3/+3
| | | | | | | | | | | | | | Rather than adding more bits to express every MMO flag you could want, just directly use the MMO flags. Also fixes using a bunch of bool arguments to getMemIntrinsicNode. On AMDGPU, buffer and image intrinsics should always have MODereferencable set, but currently there is no way to do that directly during the initial intrinsic lowering. llvm-svn: 320746
* [Hexagon] Generate HVX code for comparisons and selectsKrzysztof Parzyszek2017-12-145-7/+111
| | | | llvm-svn: 320744
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