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* [Pipeliner] Use latency to compute RecMIIKrzysztof Parzyszek2018-03-262-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch contains severals changes needed to pipeline an example that was transformed so that a Phi with a subreg is converted to copies. The pipeliner wasn't working for a couple of reasons. - The RecMII was 3 instead of 2 due to the extra copies. - Copy instructions contained a latency of 1. - The node order algorithm was not choosing the best "bottom" node, which caused an instruction to be scheduled that had a predecessor and successor already scheduled. - Updated the Hexagon Machine Scheduler to check if the node is latency bound when adding the cost for a 0-latency dependence. The RecMII was 3 because the computation looks at the number of nodes in the recurrence. The extra copy is an extra node but it shouldn't increase the latency. The new RecMII computation looks at the latency of the instructions in the recurrence. We changed the latency of the dependence of a copy to 0. The latency computation for the copy also checks the use of the copy (similar to a reg_sequence). The node order algorithm was not choosing the last instruction in the recurrence for a bottom up traversal. This was when the last instruction is a copy. A check was added when choosing the instruction to check for NodeNum if the maxASAP is the same. This means that the scheduler will not end up with another node in the recurrence that has both a predecessor and successor already scheduled. The cost computation in Hexagon Machine Scheduler adds cost when an instruction can be packetized with a zero-latency instruction. We should only do this if the schedule is latency bound. Patch by Brendon Cahoon. llvm-svn: 328542
* [Hexagon] Give priority to post-incremementing memory accesses in LSRKrzysztof Parzyszek2018-03-262-1/+8
| | | | llvm-svn: 328506
* [Hexagon] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-03-247-9/+9
| | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: kparzysz Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44857 llvm-svn: 328430
* Fix layering by moving ValueTypes.h from CodeGen to IRDavid Blaikie2018-03-233-3/+3
| | | | | | ValueTypes.h is implemented in IR already. llvm-svn: 328397
* Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie2018-03-233-3/+3
| | | | | | | | | This is used by llvm tblgen as well as by LLVM Targets, so the only common place is Support for now. (maybe we need another target for these sorts of things - but for now I'm at least making them correct & we can make them better if/when people have strong feelings) llvm-svn: 328395
* [Hexagon] Make findLoopInstr member of HexagonInstrInfoKrzysztof Parzyszek2018-03-232-3/+11
| | | | llvm-svn: 328367
* [Hexagon] Correct update of instruction offet in HW loop fixupKrzysztof Parzyszek2018-03-231-3/+7
| | | | llvm-svn: 328366
* [Hexagon] Boost profit for word-mask immediates, reduce for othersKrzysztof Parzyszek2018-03-231-10/+34
| | | | | | This avoids unnecessary splitting due to uninteresting immediates. llvm-svn: 328364
* [Hexagon] Assume all extendable branches to be of size 8 in relaxationKrzysztof Parzyszek2018-03-231-1/+8
| | | | | | | | | | | | | | The branch relaxation pass collects sizes of all instructions at the beginning, before any changes have been made. It then performs one pass over all branches to see which ones need to be extended. It does not account for the case when a previously valid branch becomes out-of-range due to relaxing other branches. This approach fixes this problem by assuming from the beginning that all extendable branches have been extended. This may cause unneeded relaxation in some cases, but avoids iteration and recomputing instruction sizes. llvm-svn: 328360
* [Hexagon] Incorrectly removing dead flag and adding kill flagKrzysztof Parzyszek2018-03-231-3/+4
| | | | | | | | | | | | The HexagonExpandCondsets pass is incorrectly removing the dead flag on a definition that is really dead, and adding a kill flag to a use that is tied to a definition. This causes an assert later during the machine scheduler when querying the live interval information. Patch by Brendon Cahoon. llvm-svn: 328357
* [Hexagon] Silence unused variable warning in Release buildsBenjamin Kramer2018-03-231-2/+2
| | | | llvm-svn: 328356
* [Hexagon] Fold offset in base+immediate loads/storesKrzysztof Parzyszek2018-03-231-9/+183
| | | | | | | | Optimize Ry = add(Rx,#n); memw(Ry+#0) = Rz => memw(Rx,#n) = Rz. Patch by Jyotsna Verma. llvm-svn: 328355
* [Hexagon] Always generate mux out of predicated transfers if possibleKrzysztof Parzyszek2018-03-231-2/+10
| | | | | | | | | | | | HexagonGenMux would collapse pairs of predicated transfers if it assumed that the predicated .new forms cannot be created. Turns out that generating mux is preferable in almost all cases. Introduce an option -hexagon-gen-mux-threshold that controls the minimum distance between the instruction defining the predicate and the later of the two transfers. If the distance is closer than the threshold, mux will not be generated. Set the threshold to 0 by default. llvm-svn: 328346
* [Hexagon] Avoid early if-conversion for one sided branchesKrzysztof Parzyszek2018-03-231-12/+19
| | | | | | Patch by Anand Kodnani. llvm-svn: 328344
* [Hexagon] Two fixes in early if-conversionKrzysztof Parzyszek2018-03-231-9/+12
| | | | | | | | | - Fix checking for vector predicate registers. - Avoid speculating llvm.lifetime.end intrinsic. Patch by Harsha Jagasia and Brendon Cahoon. llvm-svn: 328339
* [Hexagon] Copy subregisters in HexagonStoreWidenKrzysztof Parzyszek2018-03-231-8/+10
| | | | | | | | | When converting an instruction to the wider version, copy any subregisters if the original operand has a subregister. Patch by Brendon Cahoon. llvm-svn: 328333
* Fix a couple of layering violations in TransformsDavid Blaikie2018-03-212-2/+2
| | | | | | | | | | | | | Remove #include of Transforms/Scalar.h from Transform/Utils to fix layering. Transforms depends on Transforms/Utils, not the other way around. So remove the header and the "createStripGCRelocatesPass" function declaration (& definition) that is unused and motivated this dependency. Move Transforms/Utils/Local.h into Analysis because it's used by Analysis/MemoryBuiltins.cpp. llvm-svn: 328165
* [Hexagon] Generalize DAG mutation for function callsKrzysztof Parzyszek2018-03-211-18/+38
| | | | | | | | | Add barrier edges to check for any physical register. The previous code worked for the function return registers: r0/d0, v0/w0. Patch by Brendon Cahoon. llvm-svn: 328120
* [Hexagon] Add heuristic to exclude critical path cost for schedulingKrzysztof Parzyszek2018-03-202-177/+79
| | | | | | Patch by Brendon Cahoon. llvm-svn: 328022
* [Hexagon] Fix fall-through warnings in HexagonMCDuplexInfo.cppKrzysztof Parzyszek2018-03-201-4/+4
| | | | llvm-svn: 328021
* [Hexagon] Correct the computation of TopReadyCycle and BotReadyCycle of SUKrzysztof Parzyszek2018-03-201-13/+5
| | | | | | | | | TopReadyCycle and BotReadyCycle were off by one cycle when an SU is either the first instruction or the last instruction in a packet. Patch by Ikhlas Ajbar. llvm-svn: 328000
* [Hexagon] Check weak dependences when only 1 instruction is availableKrzysztof Parzyszek2018-03-201-9/+13
| | | | | | Patch by Brendon Cahoon. llvm-svn: 327997
* [Hexagon] Improve scheduling heuristic for large basic blocksKrzysztof Parzyszek2018-03-204-9/+67
| | | | | | | | | | | | | | | | | | | | This patch changes the isLatencyBound heuristic to look at the path length based upon the number of packets needed to schedule a basic block. For small basic blocks, the heuristic uses a small threshold for isLatencyBound. For large basic blocks, the heuristic uses a large threshold. The goal is to increase the priority of an instruction in a small basic block that has a large height or depth relative to the code size. For large functions, the height and depth are ignored because it increases the live range of a register and causes more spills. That is, for large functions, it is more important to schedule instructions when available, and attempt to keep the defs and uses closer together. Patch by Brendon Cahoon. llvm-svn: 327987
* [Hexagon] Fix division by zero in machine schedulerKrzysztof Parzyszek2018-03-201-1/+1
| | | | llvm-svn: 327980
* [Hexagon] Improve scheduling based on register pressureKrzysztof Parzyszek2018-03-204-77/+223
| | | | | | Patch by Brendon Cahoon. llvm-svn: 327975
* [DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"Nirav Dave2018-03-192-11/+3
| | | | | | | Reland ISel cycle checking improvements after simplifying node id invariant traversal and correcting typo. llvm-svn: 327898
* HexagonISelLowering.cpp: fix 'enum in bool context' warningHans Wennborg2018-03-191-2/+2
| | | | llvm-svn: 327832
* Revert "[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172""Nirav Dave2018-03-172-3/+11
| | | | | | as it times out building test-suite on PPC. llvm-svn: 327778
* [DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"Nirav Dave2018-03-172-11/+3
| | | | | | | Reland ISel cycle checking improvements after simplifying and reducing node id invariant traversal. llvm-svn: 327777
* [Hexagon] Avoid bank conflicts in post-RA schedulerKrzysztof Parzyszek2018-03-162-4/+14
| | | | | | | | | | Avoid scheduling two loads in such a way that they would end up in the same packet. If there is a load in a packet, try to schedule a non-load next. Patch by Brendon Cahoon. llvm-svn: 327742
* [Hexagon] Fix zero-extending non-HVX bool vectorsKrzysztof Parzyszek2018-03-162-12/+27
| | | | llvm-svn: 327712
* Remove empty fileDavid Blaikie2018-03-151-13/+0
| | | | | | | I should've deleted this in r320768 but accidentally just deleted its contents instead. llvm-svn: 327658
* [Hexagon] Counting leading/trailing bits is cheapKrzysztof Parzyszek2018-03-121-0/+4
| | | | llvm-svn: 327308
* [Hexagon] Subtarget feature to emit one instruction per packetKrzysztof Parzyszek2018-03-126-11/+34
| | | | | | | | | | | | | | | | | This adds two features: "packets", and "nvj". Enabling "packets" allows the compiler to generate instruction packets, while disabling it will prevent it and disable all optimizations that generate them. This feature is enabled by default on all subtargets. The feature "nvj" allows the compiler to generate new-value jumps and it implies "packets". It is enabled on all subtargets. The exception is made for packets with endloop instructions, since they require a certain minimum number of instructions in the packets to which they apply. Disabling "packets" will not prevent hardware loops from being generated. llvm-svn: 327302
* [Hexagon] fix 'must explicitly initialize the const member' error which ↵Sam McCall2018-03-121-2/+2
| | | | | | clang 3.8 emits llvm-svn: 327273
* Revert: r327172 "Correct load-op-store cycle detection analysis"Nirav Dave2018-03-102-3/+11
| | | | | | | | | | r327171 "Improve Dependency analysis when doing multi-node Instruction Selection" r328170 "[DAG] Enforce stricter NodeId invariant during Instruction selection" Reverting patch as NodeId invariant change is causing pathological increases in compile time on PPC llvm-svn: 327197
* [DAG] Enforce stricter NodeId invariant during Instruction selectionNirav Dave2018-03-092-11/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instruction Selection makes use of the topological ordering of nodes by node id (a node's operands have smaller node id than it) when doing cycle detection. During selection we may violate this property as a selection of multiple nodes may induce a use dependence (and thus a node id restriction) between two unrelated nodes. If a selected node has an unselected successor this may allow us to miss a cycle in detection an invalid selection. This patch fixes this by marking all unselected successors of a selected node have negated node id. We avoid pruning on such negative ids but still can reconstruct the original id for pruning. In-tree targets have been updated to replace DAG-level replacements with ISel-level ones which enforce this property. This preemptively fixes PR36312 before triggering commit r324359 relands Reviewers: craig.topper, bogner, jyknight Subscribers: arsenm, nhaehnle, javed.absar, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D43198 llvm-svn: 327170
* [Hexagon] Ignore indexed loads when handling unaligned loadsKrzysztof Parzyszek2018-03-081-3/+4
| | | | llvm-svn: 327037
* [Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned onesKrzysztof Parzyszek2018-03-0710-121/+290
| | | | | | | | | This is a follow-up to r325169, this time for all types, not just HVX vector types. Disable this by default, since it's not always safe. llvm-svn: 326915
* [Hexagon] Generate valignb for shifting shuffles (instead of vdelta)Krzysztof Parzyszek2018-03-021-11/+35
| | | | llvm-svn: 326627
* [Hexagon] Handle VACOPY in isel loweringKrzysztof Parzyszek2018-03-021-0/+1
| | | | llvm-svn: 326599
* [Hexagon] Add trap1 instructionKrzysztof Parzyszek2018-03-014-0/+60
| | | | llvm-svn: 326492
* [Hexagon] Add guest registersKrzysztof Parzyszek2018-03-015-1/+234
| | | | llvm-svn: 326450
* [Hexagon] Implement target feature +reserved-r19Krzysztof Parzyszek2018-02-283-0/+8
| | | | llvm-svn: 326364
* [Hexagon] Recognize more sign-extensions as inputs to 32x32-bit multiplyKrzysztof Parzyszek2018-02-271-2/+13
| | | | llvm-svn: 326263
* [Hexagon] Add patterns for compares of i1 valuesKrzysztof Parzyszek2018-02-271-2/+4
| | | | llvm-svn: 326220
* [Hexagon] Recognize non-immediate constants in HexagonConstPropagationKrzysztof Parzyszek2018-02-232-6/+11
| | | | llvm-svn: 325954
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-232-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
* [DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner.Amaury Sechet2018-02-231-0/+2
| | | | | | | | | | | | | | | Summary: There are transformation that change setcc into other constructs, and transform that try to reconstruct a setcc from the brcond condition. Depending on what order these transform are done, the end result differs. Most of the time, it is preferable to get a setcc as a brcond argument (and this is why brcond try to recreate the setcc in the first place) so we ensure this is done every time by also doing it at the setcc level when the only user is a brcond. Reviewers: spatel, hfinkel, niravd, craig.topper Subscribers: nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D41235 llvm-svn: 325892
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-02-221-1/+1
| | | | | | "a a" -> "a" llvm-svn: 325752
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