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* [Hexagon] Handle unnamed globals in HexagonConstExprKrzysztof Parzyszek2018-07-231-3/+15
| | | | | | Instead of comparing names, compare positions in the parent module. llvm-svn: 337723
* [Hexagon] Avoid introducing calls into coalesced range of HVX vector pairsKrzysztof Parzyszek2018-07-132-0/+54
| | | | | | | | | | | | | If an HVX vector register is to be coalesced into a vector pair, make sure that the vector pair will not have a function call in its live range, unless it already had one. All HVX vector registers are volatile, so any vector register live across a function call will have to be spilled. If a vector needs to be spilled, and it's coalesced into a vector pair then the whole pair will need to be spilled (even if only a part of it is live), taking extra stack space. llvm-svn: 337073
* [TableGen] Support multi-alternative pattern fragmentsUlrich Weigand2018-07-131-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A TableGen instruction record usually contains a DAG pattern that will describe the SelectionDAG operation that can be implemented by this instruction. However, there will be cases where several different DAG patterns can all be implemented by the same instruction. The way to represent this today is to write additional patterns in the Pattern (or usually Pat) class that map those extra DAG patterns to the instruction. This usually also works fine. However, I've noticed cases where the current setup seems to require quite a bit of extra (and duplicated) text in the target .td files. For example, in the SystemZ back-end, there are quite a number of instructions that can implement an "add-with-overflow" operation. The same instructions also need to be used to implement just plain addition (simply ignoring the extra overflow output). The current solution requires creating extra Pat pattern for every instruction, duplicating the information about which particular add operands map best to which particular instruction. This patch enhances TableGen to support a new PatFrags class, which can be used to encapsulate multiple alternative patterns that may all match to the same instruction. It operates the same way as the existing PatFrag class, except that it accepts a list of DAG patterns to match instead of just a single one. As an example, we can now define a PatFrags to match either an "add-with-overflow" or a regular add operation: def z_sadd : PatFrags<(ops node:$src1, node:$src2), [(z_saddo node:$src1, node:$src2), (add node:$src1, node:$src2)]>; and then use this in the add instruction pattern: defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; These SystemZ target changes are implemented here as well. Note that PatFrag is now defined as a subclass of PatFrags, which means that some users of internals of PatFrag need to be updated. (E.g. instead of using PatFrag.Fragment you now need to use !head(PatFrag.Fragments).) The implementation is based on the following main ideas: - InlinePatternFragments may now replace each original pattern with several result patterns, not just one. - parseInstructionPattern delays calling InlinePatternFragments and InferAllTypes. Instead, it extracts a single DAG match pattern from the main instruction pattern. - Processing of the DAG match pattern part of the main instruction pattern now shares most code with processing match patterns from the Pattern class. - Direct use of main instruction patterns in InferFromPattern and EmitResultInstructionAsOperand is removed; everything now operates solely on DAG match patterns. Reviewed by: hfinkel Differential Revision: https://reviews.llvm.org/D48545 llvm-svn: 336999
* [CodeGen] Emit more precise AssertZext/AssertSext nodes.Eli Friedman2018-07-111-1/+1
| | | | | | | | | | | | This is marginally helpful for removing redundant extensions, and the code is easier to read, so it seems like an all-around win. In the new test i8-phi-ext.ll, we used to emit an AssertSext i8; now we emit an AssertZext i2, which allows the extension of the return value to be eliminated. Differential Revision: https://reviews.llvm.org/D49004 llvm-svn: 336868
* [Hexagon] Add implicit uses even when untied explicit uses are presentKrzysztof Parzyszek2018-07-101-2/+6
| | | | | | | | | | | | | | | | | | An explicit untied use is not sufficient to maintain liveness of a register redefined in a predicated instruction. For example %1 = COPY %0 ... %1 = A2_paddif %2, %1, 1 could become $r1 = COPY $r0 ... $r1 = A2_paddif $p0, $r1, 1 and later $r1 = COPY $r0 ;; this is not really dead! ... $r1 = A2_paddif $p0, $r0, 1 llvm-svn: 336662
* [Hexagon] Remove unused instruction itineraties, NFCKrzysztof Parzyszek2018-06-291-680/+0
| | | | llvm-svn: 335975
* [Hexagon] Add a "generic" cpuBrendon Cahoon2018-06-264-1/+7
| | | | | | | | | | Add the generic processor for Hexagon so that it can be used with 3rd party programs that create a back-end with the "generic" CPU. This patch also enables the JIT for Hexagon. Differential Revision: https://reviews.llvm.org/D48571 llvm-svn: 335641
* [Hexagon] Remove 'T' from HasVNN predicates, NFCKrzysztof Parzyszek2018-06-2014-258/+258
| | | | | | Patch by Sumanth Gundapaneni. llvm-svn: 335124
* [Hexagon] Fix the value of HexagonII::TypeCVI_FIRSTKrzysztof Parzyszek2018-06-191-1/+1
| | | | | | | | | This value is the first vector instruction type in numerical order. The previous value was incorrect, leaving TypeCVI_GATHER outside of the range for vector instructions. This caused vector .new instructions to be incorrectly encoded in the presence of gather. llvm-svn: 335065
* [Hexagon] Enforce restrictions on packetizing cache instructionsKrzysztof Parzyszek2018-06-191-0/+4
| | | | llvm-svn: 335061
* [DAGCombiner] Recognize more patterns for ABSKrzysztof Parzyszek2018-06-122-16/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D47831 llvm-svn: 334553
* [Hexagon] Make floating point operations expensive for vectorizationKrzysztof Parzyszek2018-06-122-6/+35
| | | | llvm-svn: 334508
* [SelectionDAG] Provide default expansion for rotatesKrzysztof Parzyszek2018-06-123-0/+32
| | | | | | | | | | | | | Implement default legalization of rotates: either in terms of the rotation in the opposite direction (if legal), or in terms of shifts and ors. Implement generating of rotate instructions for Hexagon. Hexagon only supports rotates by an immediate value, so implement custom lowering of ROTL/ROTR on Hexagon. If a rotate is not legal, use the default expansion. Differential Revision: https://reviews.llvm.org/D47725 llvm-svn: 334497
* [Hexagon] Late predicate producers cannot be used as dot-new sourcesKrzysztof Parzyszek2018-06-111-4/+23
| | | | llvm-svn: 334426
* [Hexagon] Implement vector-pair zero as V6_vsubw_dvKrzysztof Parzyszek2018-06-063-4/+17
| | | | llvm-svn: 334123
* [Hexagon] Split CTPOP of vector pairsKrzysztof Parzyszek2018-06-061-0/+1
| | | | llvm-svn: 334109
* [MC] Pass MCSubtargetInfo to fixupNeedsRelaxation and applyFixupPeter Smith2018-06-061-5/+7
| | | | | | | | | | | | | | | | | | On targets like Arm some relaxations may only be performed when certain architectural features are available. As functions can be compiled with differing levels of architectural support we must make a judgement on whether we can relax based on the MCSubtargetInfo for the function. This change passes through the MCSubtargetInfo for the function to fixupNeedsRelaxation so that the decision on whether to relax can be made per function. In this patch, only the ARM backend makes use of this information. We must also pass the MCSubtargetInfo to applyFixup because some fixups skip error checking on the assumption that relaxation has occurred, to prevent code-generation errors applyFixup must see the same MCSubtargetInfo as fixupNeedsRelaxation. Differential Revision: https://reviews.llvm.org/D44928 llvm-svn: 334078
* [Hexagon] Add pattern to generate 64-bit neg instructionKrzysztof Parzyszek2018-06-051-4/+5
| | | | llvm-svn: 334043
* [Hexagon] Add more patterns for generating abs/absp instructionsKrzysztof Parzyszek2018-06-051-5/+15
| | | | llvm-svn: 334038
* [Hexagon] Minor cleanups in isel loweringKrzysztof Parzyszek2018-06-051-9/+8
| | | | llvm-svn: 334015
* Move Analysis/Utils/Local.h back to TransformsDavid Blaikie2018-06-042-2/+2
| | | | | | | | | | Review feedback from r328165. Split out just the one function from the file that's used by Analysis. (As chandlerc pointed out, the original change only moved the header and not the implementation anyway - which was fine for the one function that was used (since it's a template/inlined in the header) but not in general) llvm-svn: 333954
* [Hexagon] Avoid UB when shifting unsigned integer left by 32Krzysztof Parzyszek2018-06-011-3/+4
| | | | llvm-svn: 333771
* [Hexagon] Select HVX code for vector CTPOP, CTLZ, and CTTZKrzysztof Parzyszek2018-06-013-15/+80
| | | | llvm-svn: 333760
* [SelectionDAG] Expand UADDO/USUBO into ADD/SUBCARRY if legal for targetKrzysztof Parzyszek2018-06-014-5/+48
| | | | | | | | | Additionally, implement handling of ADD/SUBCARRY on Hexagon, utilizing the UADDO/USUBO expansion. Differential Revision: https://reviews.llvm.org/D47559 llvm-svn: 333751
* Set ADDE/ADDC/SUBE/SUBC to expand by defaultAmaury Sechet2018-06-011-26/+3
| | | | | | | | | | | | | | | Summary: They've been deprecated in favor of UADDO/ADDCARRY or USUBO/SUBCARRY for a while. Target that uses these opcodes are changed in order to ensure their behavior doesn't change. Reviewers: efriedma, craig.topper, dblaikie, bkramer Subscribers: jholewinski, arsenm, jyknight, sdardis, nemanjai, nhaehnle, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D47422 llvm-svn: 333748
* [Hexagon] Use vector align-left when shift amount fits in 3 bitsKrzysztof Parzyszek2018-05-301-6/+11
| | | | | | | This saves an instruction because for align-right the shift amount would need to be put in a register first. llvm-svn: 333543
* Replace AA's uses of uint64_t with LocationSize; NFC.George Burgess IV2018-05-251-1/+1
| | | | | | | | | | | | | | | | The uint64_ts that we pass around AA to represent MemoryLocation sizes are logically an Optional<uint64_t>. In D44748, we want to add an extra 'imprecise' bit to this Optional<uint64_t> to represent whether a given MemoryLocation size is an upper-bound or an exact size. For more context on why, please see D44748. That patch is quite large, but reviewers seem to be OK with the approach. In D45581 (my first attempt to split 'noise' out of D44748), reames asked that I land a precursor that is solely replacing uint64_t with LocationSize, which starts out as `using LocationSize = uint64_t;`. He also gave me the OK to submit this rename without further review. llvm-svn: 333314
* [Hexagon] Fix packing source vectors in shufflevector selection Krzysztof Parzyszek2018-05-251-3/+9
| | | | | | | | When the shuffle mask selected a subvector of the second input vector, and aligning of the source was performed, the shuffle mask was updated incorrectly, resulting in an ICE further in the selection process. llvm-svn: 333279
* [Hexagon] Add patterns for accumulating HVX comparesKrzysztof Parzyszek2018-05-222-122/+148
| | | | llvm-svn: 333009
* MC: Separate creating a generic object writer from creating a target object ↵Peter Collingbourne2018-05-213-12/+9
| | | | | | | | | | | | | writer. NFCI. With this we gain a little flexibility in how the generic object writer is created. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47045 llvm-svn: 332868
* MC: Change MCAsmBackend::writeNopData() to take a raw_ostream instead of an ↵Peter Collingbourne2018-05-211-7/+7
| | | | | | | | | | | | | MCObjectWriter. NFCI. To make this work I needed to add an endianness field to MCAsmBackend so that writeNopData() implementations know which endianness to use. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47035 llvm-svn: 332857
* Fix up a few grammar issues.Eric Christopher2018-05-211-1/+1
| | | | llvm-svn: 332835
* Support: Simplify endian stream interface. NFCI.Peter Collingbourne2018-05-181-1/+1
| | | | | | | | | | | | Provide some free functions to reduce verbosity of endian-writing a single value, and replace the endianness template parameter with a field. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47032 llvm-svn: 332757
* MC: Change the streamer ctors to take an object writer instead of a stream. ↵Peter Collingbourne2018-05-183-11/+14
| | | | | | | | | | | | | | NFCI. The idea is that a client that wants split dwarf would create a specific kind of object writer that creates two files, and use it to create the streamer. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47050 llvm-svn: 332749
* [Hexagon] Generate post-increment for floating point typesBrendon Cahoon2018-05-183-4/+11
| | | | | | | | | | The code that generates post-increments for Hexagon considered integer values only. This patch adds support to generate them for floating point values, f32 and f64. Differential Revision: https://reviews.llvm.org/D47036 llvm-svn: 332748
* [RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvancedShiva Chen2018-05-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
* [Hexagon] Use addAliasForDirective for data directivesAlex Bradbury2018-05-171-39/+4
| | | | | | | | | | | Data directives such as .word, .half, .hword are currently parsed using HexagonAsmParser::ParseDirectiveValue which effectively duplicates logic from AsmParser::parseDirectiveValue. This patch deletes that duplicated logic in favour of using addAliasForDirective. Differential Revision: https://reviews.llvm.org/D46999 llvm-svn: 332607
* [Hexagon] Fix the order of operands when selecting QCATKrzysztof Parzyszek2018-05-161-2/+2
| | | | llvm-svn: 332526
* [Hexagon] Mark HVX vector predicate bitwise ops as legal, add patternsKrzysztof Parzyszek2018-05-162-35/+73
| | | | llvm-svn: 332525
* Fix up a misleading format warning.Eric Christopher2018-05-161-1/+1
| | | | llvm-svn: 332521
* [Hexagon] Remove unused function from subtargetKrzysztof Parzyszek2018-05-151-8/+0
| | | | llvm-svn: 332369
* [Hexagon] Remove unused flag from subtarget and (non)corresponding testKrzysztof Parzyszek2018-05-153-8/+0
| | | | llvm-svn: 332365
* [Hexagon] Add a target feature to control using small data sectionKrzysztof Parzyszek2018-05-144-16/+20
| | | | llvm-svn: 332292
* [Hexagon] Add a target feature for generating new-value storesKrzysztof Parzyszek2018-05-143-6/+18
| | | | llvm-svn: 332290
* [Hexagon] Add a target feature for memop generationKrzysztof Parzyszek2018-05-144-31/+32
| | | | llvm-svn: 332285
* [Hexagon] Avoid predicate copies to integer registers from store-lockedKrzysztof Parzyszek2018-05-141-0/+15
| | | | llvm-svn: 332260
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-1433-500/+532
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [Hexagon] Add patterns for vector shift-and-accumulateKrzysztof Parzyszek2018-05-091-0/+5
| | | | llvm-svn: 331918
* [Hexagon] Check the end of the correct container (fix typo)Krzysztof Parzyszek2018-05-091-3/+1
| | | | llvm-svn: 331907
* [Hexagon] Fix sanitizer error about using -1u in variable of enum typeKrzysztof Parzyszek2018-05-091-4/+4
| | | | llvm-svn: 331887
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