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* Annotate possibly unintended fallthroughs in Hexagon MC code, NFCReid Kleckner2018-11-011-0/+6
| | | | | | | | | | | | | | | | Clang's -Wimplicit-fallthrough check fires on these switch cases. GCC does not warn when a case body that ends in a switch falls through to a case label of an outer switch. It's not clear if these fall throughs are truly intended. The Hexagon tests pass regardless of whether these case blocks fall through or break. For now, I have applied the intended fallthrough annotation macro with a FIXME comment to unblock enabling the warning. I will send a follow-up patch that converts them to breaks to the Hexagon maintainers. llvm-svn: 345878
* [Hexagon] Fix MO_JumpTable const extender conversionReid Kleckner2018-11-011-0/+1
| | | | | | | | | | Previously this case fell through to unreachable, so it is clearly not covered by any test case in LLVM. It may be dynamically unreachable, in fact. However, if it were to run, this is what it would logically do. The assert suggests that the intended behavior was not to allow folding offsets from jump table indices, which makes sense. llvm-svn: 345868
* [Hexagon] Make sure not to use GP-relative addressing with PICKrzysztof Parzyszek2018-10-313-4/+10
| | | | | | | Make sure that -relocation-model=pic prevents use of GP-relative addressing modes. llvm-svn: 345731
* [LV] Support vectorization of interleave-groups that require an epilog underDorit Nuzman2018-10-312-4/+7
| | | | | | | | | | | | | | | | | | | | | | optsize using masked wide loads Under Opt for Size, the vectorizer does not vectorize interleave-groups that have gaps at the end of the group (such as a loop that reads only the even elements: a[2*i]) because that implies that we'll require a scalar epilogue (which is not allowed under Opt for Size). This patch extends the support for masked-interleave-groups (introduced by D53011 for conditional accesses) to also cover the case of gaps in a group of loads; Targets that enable the masked-interleave-group feature don't have to invalidate interleave-groups of loads with gaps; they could now use masked wide-loads and shuffles (if that's what the cost model selects). Reviewers: Ayal, hsaito, dcaballe, fhahn Reviewed By: Ayal Differential Revision: https://reviews.llvm.org/D53668 llvm-svn: 345705
* Revert r345169 [along with its llvm counterpart r345170] as it makes Halide ↵Alina Sbirlea2018-10-271-1/+1
| | | | | | builds timeout. llvm-svn: 345447
* [Hexagon] Add missing assignment to Itinerary in Call_nrBrendon Cahoon2018-10-271-0/+1
| | | | | | | | | | | | The class definition for Call_nr has the itinerary as a parameter, but the value is never assigned to the Itinerary field for the instruction. This means the compiler is unable to schedule and packetize the instruction correctly because these instrution will not have any resource descritions. I don't have a specific test case, but the ps_call_nr.ll test failed with a proposed patch. llvm-svn: 345442
* [Hexagon] Flip hexagon-autohvx to be true by defaultKrzysztof Parzyszek2018-10-241-1/+1
| | | | | | | | | | | This will allow other generators of LLVM IR to use the auto-vectorizer without having to change that flag. Note: on its own, this patch will enable auto-vectorization on Hexagon in all cases, regardless of the -fvectorize flag. There is a companion clang patch that together with this one forms an NFC for clang users. llvm-svn: 345169
* [Hexagon] Remove support for V4Krzysztof Parzyszek2018-10-1923-757/+567
| | | | llvm-svn: 344791
* Use llvm::{all,any,none}_of instead std::{all,any,none}_of. NFCFangrui Song2018-10-191-1/+1
| | | | llvm-svn: 344774
* recommit 344472 after fixing build failure on ARM and PPC.Dorit Nuzman2018-10-142-4/+4
| | | | llvm-svn: 344475
* revert 344472 due to failures.Dorit Nuzman2018-10-142-4/+4
| | | | llvm-svn: 344473
* [IAI,LV] Add support for vectorizing predicated strided accesses using maskedDorit Nuzman2018-10-142-4/+4
| | | | | | | | | | | | | | | | | | | | | | | interleave-group The vectorizer currently does not attempt to create interleave-groups that contain predicated loads/stores; predicated strided accesses can currently be vectorized only using masked gather/scatter or scalarization. This patch makes predicated loads/stores candidates for forming interleave-groups during the Loop-Vectorizer's analysis, and adds the proper support for masked-interleave- groups to the Loop-Vectorizer's planning and transformation stages. The patch also extends the TTI API to allow querying the cost of masked interleave groups (which each target can control); Targets that support masked vector loads/ stores may choose to enable this feature and allow vectorizing predicated strided loads/stores using masked wide loads/stores and shuffles. Reviewers: Ayal, hsaito, dcaballe, fhahn, javed.absar Reviewed By: Ayal Differential Revision: https://reviews.llvm.org/D53011 llvm-svn: 344472
* [Hexagon] Restrict compound instructions with constant value.Sumanth Gundapaneni2018-10-111-10/+27
| | | | | | | | | | Having a constant value operand in the compound instruction is not always profitable. This patch improves coremark by ~4% on Hexagon. Differential Revision: https://reviews.llvm.org/D53152 llvm-svn: 344284
* [Hexagon] Eliminate potential sources of non-determinism in HCEKrzysztof Parzyszek2018-10-111-9/+33
| | | | | | | | | Also, avoid comparing GUIDs when ordering global addresses, because source file location can cause different GUID to be calculated. As a result, a pair of symbols can compare "less" in one directory, but "greater" in another. llvm-svn: 344271
* Replace most users of UnknownSize with LocationSize::unknown(); NFCGeorge Burgess IV2018-10-101-1/+1
| | | | | | | | | | | | Moving away from UnknownSize is part of the effort to migrate us to LocationSizes (e.g. the cleanup promised in D44748). This doesn't entirely remove all of the uses of UnknownSize; some uses require tweaks to assume that UnknownSize isn't just some kind of int. This patch is intended to just be a trivial replacement for all places where LocationSize::unknown() will Just Work. llvm-svn: 344186
* [TargetRegisterInfo] Remove temporary hook enableMultipleCopyHints()Jonas Paulsson2018-10-051-2/+0
| | | | | | | | | | | | Finally all targets are enabling multiple regalloc hints, so the hook to disable this can now be removed. NFC. Review: Simon Pilgrim https://reviews.llvm.org/D52316 llvm-svn: 343851
* [Hexagon] Fix extracting subvectors of non-HVX vNi1Krzysztof Parzyszek2018-10-021-1/+2
| | | | | | Patch by Brendon Cahoon. llvm-svn: 343596
* [Hexagon] Remove incorrect pattern for swizKrzysztof Parzyszek2018-10-011-8/+0
| | | | | | | | | | | | The pattern had a couple of problems: - It was checking for loads of bytes in the reverse order to what it should have been looking for. - It would replace loads of bytes with a load of a word without making sure that the alignment was correct. Thanks to Eli Friedman for pointing it out. llvm-svn: 343514
* llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)Fangrui Song2018-09-276-11/+10
| | | | | | | | | | | | Summary: The convenience wrapper in STLExtras is available since rL342102. Reviewers: dblaikie, javed.absar, JDevlieghere, andreadb Subscribers: MatzeB, sanjoy, arsenm, dschuff, mehdi_amini, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, eraman, aheejin, kbarton, JDevlieghere, javed.absar, gbedwell, jrtc27, mgrang, atanasyan, steven_wu, george.burgess.iv, dexonsmith, kristina, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D52573 llvm-svn: 343163
* [Hexagon] Avoid functions with exception handling in HexagonConstExtendersKrzysztof Parzyszek2018-09-211-0/+5
| | | | | | | The constant-extender optimization does a form of code motion, which is complicated in the presence of exception handling. llvm-svn: 342751
* [AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IRAlex Bradbury2018-09-192-4/+8
| | | | | | | | | | | | | | | | | This involves changing the shouldExpandAtomicCmpXchgInIR interface, but I have updated the in-tree backends using this hook (ARM, AArch64, Hexagon) so they will see no functional change. Previously this hook returned bool, but it now returns AtomicExpansionKind. This hook allows targets to select how a given cmpxchg is to be expanded. D48131 uses this to expand part-word cmpxchg to a target-specific intrinsic. See my associated RFC for more info on the motivation for this change <http://lists.llvm.org/pipermail/llvm-dev/2018-June/123993.html>. Differential Revision: https://reviews.llvm.org/D48130 llvm-svn: 342550
* ScheduleDAG: Cleanup dumping code; NFCMatthias Braun2018-09-191-4/+3
| | | | | | | | | | | | - Instead of having both `SUnit::dump(ScheduleDAG*)` and `ScheduleDAG::dumpNode(ScheduleDAG*)`, just keep the latter around. - Add `ScheduleDAG::dump()` and avoid code duplication in several places. Implement it for different ScheduleDAG variants. - Add `ScheduleDAG::dumpNodeName()` in favor of the `SUnit::print()` functions. They were only ever used for debug dumping and putting the function into ScheduleDAG is consistent with the `dumpNode()` change. llvm-svn: 342520
* [Hexagon] Use shuffles when lowering "gather" shufflevectorsKrzysztof Parzyszek2018-09-121-0/+70
| | | | | | | | Shufflevector instructions in LLVM IR that extract a subset of elements of a longer input into a shorter vector can be done using VECTOR_SHUFFLEs. This will avoid expanding them into constly extracts and inserts. llvm-svn: 342091
* [Hexagon] Improve the selection algorithm in scalarizeShuffleKrzysztof Parzyszek2018-09-121-22/+89
| | | | | | Use topological ordering for newly generated nodes. llvm-svn: 342090
* [Hexagon] Use legalized type for extracted elements in scalarizeShuffleKrzysztof Parzyszek2018-09-121-2/+4
| | | | | | | | | Scalarization of a shuffle will break up the source vectors into individual elements, and use them to assemble the resulting vector. An element type of a legal vector type may not necessarily be a legal scalar type, so make sure that the extracted values are extended to a legal scalar type. llvm-svn: 342079
* [Hexagon] Split large offsets into properly aligned addendsKrzysztof Parzyszek2018-09-101-0/+9
| | | | llvm-svn: 341851
* [Target] Untangle disassemblersBenjamin Kramer2018-09-104-29/+28
| | | | | | | Disassemblers cannot depend on main target headers. The same is true for MCTargetDesc, but there's a lot more cleanup needed for that. llvm-svn: 341822
* Don't create a temporary vector of loop blocks just to iterate over them.Benjamin Kramer2018-09-101-8/+6
| | | | | | Loop's getBlocks returns an ArrayRef. llvm-svn: 341821
* Add support for getRegisterByName.Sid Manning2018-09-072-0/+16
| | | | | | | | Support required to build the Hexagon Linux kernel. Differential Revision: https://reviews.llvm.org/D51363 llvm-svn: 341658
* [Hexagon] Ignore unnamed globals in HexagonConstExtendersKrzysztof Parzyszek2018-09-051-15/+8
| | | | | | | | | This replaces r337723. The global list in the module can be huge with LTO, plus the module can change between different invocations of the pass, so there is no easy way to deterministically cache the ordering (especially in the presence of multiple threads). llvm-svn: 341478
* Remove FrameAccess struct from hasLoadFromStackSlotSander de Smalen2018-09-052-4/+4
| | | | | | | | | | | | | | This removes the FrameAccess struct that was added to the interface in D51537, since the PseudoValue from the MachineMemoryOperand can be safely casted to a FixedStackPseudoSourceValue. Reviewers: MatzeB, thegameg, javed.absar Reviewed By: thegameg Differential Revision: https://reviews.llvm.org/D51617 llvm-svn: 341454
* [Hexagon] Don't packetize new-value stores with any other storesKrzysztof Parzyszek2018-09-041-0/+7
| | | | llvm-svn: 341409
* Revert [Hexagon] Add support for getRegisterByName.Sid Manning2018-09-032-49/+0
| | | | | | Support required to build the Hexagon Linux kernel. llvm-svn: 341331
* Extend hasStoreToStackSlot with list of FI accesses.Sander de Smalen2018-09-032-16/+16
| | | | | | | | | | | | | | | | | | For instructions that spill/fill to and from multiple frame-indices in a single instruction, hasStoreToStackSlot and hasLoadFromStackSlot should return an array of accesses, rather than just the first encounter of such an access. This better describes FI accesses for AArch64 (paired) LDP/STP instructions. Reviewers: t.p.northover, gberry, thegameg, rengolin, javed.absar, MatzeB Reviewed By: MatzeB Differential Revision: https://reviews.llvm.org/D51537 llvm-svn: 341301
* [Hexagon] Don't access non-existent instructionsKrzysztof Parzyszek2018-08-311-1/+1
| | | | llvm-svn: 341264
* [Hexagon] Add support for getRegisterByName.Sid Manning2018-08-312-0/+49
| | | | | | | | Support required to build the Hexagon Linux kernel. Differential Revision: https://reviews.llvm.org/D51363 llvm-svn: 341238
* [Hexagon] Check validity of register class when generating bitsplitKrzysztof Parzyszek2018-08-301-0/+4
| | | | llvm-svn: 341137
* [Hexagon] Enable interleaving in loop vectorizerKrzysztof Parzyszek2018-08-222-2/+7
| | | | llvm-svn: 340447
* [Hexagon] Remove unused functions from HexagonInstPrinter, NFCKrzysztof Parzyszek2018-08-172-124/+8
| | | | llvm-svn: 340081
* [Hexagon] Expand vgather pseudos during packetizationKrzysztof Parzyszek2018-08-177-209/+123
| | | | | | This will allow packetizing the vgather expansion with other instructions. llvm-svn: 340028
* [MI] Change the array of `MachineMemOperand` pointers to beChandler Carruth2018-08-165-53/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a generically extensible collection of extra info attached to a `MachineInstr`. The primary change here is cleaning up the APIs used for setting and manipulating the `MachineMemOperand` pointer arrays so chat we can change how they are allocated. Then we introduce an extra info object that using the trailing object pattern to attach some number of MMOs but also other extra info. The design of this is specifically so that this extra info has a fixed necessary cost (the header tracking what extra info is included) and everything else can be tail allocated. This pattern works especially well with a `BumpPtrAllocator` which we use here. I've also added the basic scaffolding for putting interesting pointers into this, namely pre- and post-instruction symbols. These aren't used anywhere yet, they're just there to ensure I've actually gotten the data structure types correct. I'll flesh out support for these in a subsequent patch (MIR dumping, parsing, the works). Finally, I've included an optimization where we store any single pointer inline in the `MachineInstr` to avoid the allocation overhead. This is expected to be the overwhelmingly most common case and so should avoid any memory usage growth due to slightly less clever / dense allocation when dealing with >1 MMO. This did require several ergonomic improvements to the `PointerSumType` to reasonably support the various usage models. This also has a side effect of freeing up 8 bits within the `MachineInstr` which could be repurposed for something else. The suggested direction here came largely from Hal Finkel. I hope it was worth it. ;] It does hopefully clear a path for subsequent extensions w/o nearly as much leg work. Lots of thanks to Reid and Justin for careful reviews and ideas about how to do all of this. Differential Revision: https://reviews.llvm.org/D50701 llvm-svn: 339940
* [SDAG] Remove the reliance on MI's allocation strategy forChandler Carruth2018-08-142-17/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `MachineMemOperand` pointers attached to `MachineSDNodes` and instead have the `SelectionDAG` fully manage the memory for this array. Prior to this change, the memory management was deeply confusing here -- The way the MI was built relied on the `SelectionDAG` allocating memory for these arrays of pointers using the `MachineFunction`'s allocator so that the raw pointer to the array could be blindly copied into an eventual `MachineInstr`. This creates a hard coupling between how `MachineInstr`s allocate their array of `MachineMemOperand` pointers and how the `MachineSDNode` does. This change is motivated in large part by a change I am making to how `MachineFunction` allocates these pointers, but it seems like a layering improvement as well. This would run the risk of increasing allocations overall, but I've implemented an optimization that should avoid that by storing a single `MachineMemOperand` pointer directly instead of allocating anything. This is expected to be a net win because the vast majority of uses of these only need a single pointer. As a side-effect, this makes the API for updating a `MachineSDNode` and a `MachineInstr` reasonably different which seems nice to avoid unexpected coupling of these two layers. We can map between them, but we shouldn't be *surprised* at where that occurs. =] Differential Revision: https://reviews.llvm.org/D50680 llvm-svn: 339740
* [Hexagon] Silence -Wuninitialized warning from GCC 5.4, NFCKrzysztof Parzyszek2018-08-131-0/+4
| | | | | | | | Patch by Kim Gräsman. Differential Revision: https://reviews.llvm.org/D50623 llvm-svn: 339576
* Check for tied operandsSid Manning2018-08-131-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D50592 llvm-svn: 339567
* [Hexagon] Map ISD::TRAP to J2_trap0(#0)Krzysztof Parzyszek2018-08-093-15/+20
| | | | llvm-svn: 339365
* [Hexagon] Diagnose misaligned absolute loads and storesKrzysztof Parzyszek2018-08-083-92/+210
| | | | | | Differential Revision: https://reviews.llvm.org/D50405 llvm-svn: 339272
* [Hexagon] Allow use of gather intrinsics even with no-packetsKrzysztof Parzyszek2018-08-072-9/+0
| | | | | | | | | Vgather requires must be in a packet with a store, which contradicts the no-packets feature. As a consequence, gather/scatter could not be used with no-packets. Relax this, and allow gather packets as exceptions to the no-packets requirements. llvm-svn: 339177
* [Hexagon] Simplify CFG after atomic expansionKrzysztof Parzyszek2018-08-021-0/+7
| | | | | | | | | | This will remove suboptimal branching from the generated ll/sc loops. The extra simplification pass affects a lot of testcases, which have been modified to accommodate this change: either by modifying the test to become immune to the CFG simplification, or (less preferablt) by adding option -hexagon-initial-cfg-clenaup=0. llvm-svn: 338774
* [Hexagon] Simplify A4_rcmp[n]eqi R, 0Krzysztof Parzyszek2018-07-303-3/+157
| | | | | | | Consider cases when register R is known to be zero/non-zero, or when it is defined by a C2_muxii instruction. llvm-svn: 338251
* [Hexagon] Properly scale bit index when extracting elements from vNi1Krzysztof Parzyszek2018-07-251-1/+3
| | | | | | | | For example v = <2 x i1> is represented as bbbbaaaa in a predicate register, where b = v[1], a = v[0]. Extracting v[1] is equivalent to extracting bit 4 from the predicate register. llvm-svn: 337934
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