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* [RDF] Improve handling of inline-asmKrzysztof Parzyszek2016-04-281-4/+5
| | | | | | | - Keep implicit defs from inline-asm instructions. - Treat register references from inline-asm as fixed. llvm-svn: 267936
* [RDF] Add option to keep dead phi nodes in DFGKrzysztof Parzyszek2016-04-283-4/+15
| | | | | | | | | | Dead phi nodes are needed for code motion (such as copy propagation), where a new use would be placed in a location that would be dominated by a dead phi. Such a transformation is not legal for copy propagation, and the existence of the phi would prevent it, but if the phi is not there, it may appear to be valid. llvm-svn: 267932
* [Hexagon] Add instruction aliases for vector unsigned compare-equalKrzysztof Parzyszek2016-04-281-0/+65
| | | | | | Unsigned compare-equal instructions are mapped to signed compare-equal. llvm-svn: 267925
* [Hexagon] Define certain aliases for vector instructionsKrzysztof Parzyszek2016-04-283-0/+43
| | | | | | | | | Specifically: Vd = #0 -> Vd = vxor(Vd, Vd) Vdd = #0 -> Vdd.w = vsub(Vdd.w, Vdd.w) Vdd = Vss -> Vdd = vcombine(Vss.H, Vss.L) llvm-svn: 267901
* [Hexagon] Handle double-vector registers as new-value producersKrzysztof Parzyszek2016-04-283-3/+42
| | | | | | Patch by Colin LeMahieu. llvm-svn: 267897
* [RDF] Handle undefined registers in RDF copy propagationKrzysztof Parzyszek2016-04-281-1/+6
| | | | | | | When updating the graph, make sure that new uses without reaching defs are handled correctly. llvm-svn: 267891
* [CodeGen] Default CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF to Expand in ↵Craig Topper2016-04-281-10/+1
| | | | | | TargetLoweringBase. This is what the majority of the targets want and removes a bunch of code. Set it to Legal explicitly in the few cases where that's the desired behavior. llvm-svn: 267853
* [Hexagon] Merging nops in to previous packet rather than always creating a ↵Colin LeMahieu2016-04-271-17/+69
| | | | | | new one. llvm-svn: 267798
* Add optimization bisect opt-in calls for Hexagon passesAndrew Kaylor2016-04-2618-1/+52
| | | | | | Differential Revision: http://reviews.llvm.org/D19509 llvm-svn: 267593
* [Hexagon] Few fixes for exception handlingKrzysztof Parzyszek2016-04-252-1/+2
| | | | llvm-svn: 267469
* [Hexagon] Register save/restore functions do not follow regular conventionsKrzysztof Parzyszek2016-04-254-45/+51
| | | | | | Do not mark them as modifying any of the volatile registers by default. llvm-svn: 267433
* [Hexagon] Correctly set "Flags" in ELF headerKrzysztof Parzyszek2016-04-251-3/+7
| | | | llvm-svn: 267397
* Fix a couple assertions that can never fire because they just contained the ↵Craig Topper2016-04-241-1/+1
| | | | | | text string which always evaluates to true. Add a ! so they'll evaluate to false. llvm-svn: 267312
* [Hexagon] Set ctlz_zero_undef/cttz_zero_undef to Expand so LegalizeDAG will ↵Craig Topper2016-04-233-16/+8
| | | | | | convert them to ctlz/cttz. Remove the now unneccessary isel patterns. NFC llvm-svn: 267266
* [Hexagon] Use common Pat classes for selecting code for intrinsicsKrzysztof Parzyszek2016-04-224-332/+361
| | | | llvm-svn: 267178
* [Hexagon] Properly close live range in HexagonBlockRangesKrzysztof Parzyszek2016-04-221-1/+1
| | | | llvm-svn: 267173
* [Hexagon] Teach mux expansion how to deal with undef predicatesKrzysztof Parzyszek2016-04-221-5/+13
| | | | llvm-svn: 267165
* [Hexagon] Add definitions for trap/pause instructionsKrzysztof Parzyszek2016-04-221-0/+21
| | | | | | Also add tests for other instructions from HexagonSystemInst.td. llvm-svn: 267162
* [Hexagon] Properly recognize register alt namesKrzysztof Parzyszek2016-04-213-38/+47
| | | | llvm-svn: 267038
* [Hexagon] Expand handling of the small-data/bss sectionKrzysztof Parzyszek2016-04-214-67/+367
| | | | llvm-svn: 267034
* [Hexagon] Add -mv.. options to override CPU selectionKrzysztof Parzyszek2016-04-201-3/+39
| | | | | | | This is for compatibility with scripts that use -mv5, etc. with the assembler. llvm-svn: 266918
* [Hexagon] Fix handling of lcomm directiveKrzysztof Parzyszek2016-04-201-7/+12
| | | | | | Patch by Colin LeMahieu. llvm-svn: 266882
* [RDF] Consider register as live if any alias is liveKrzysztof Parzyszek2016-04-201-2/+2
| | | | | | This only affects the recomputation of kill flags. llvm-svn: 266875
* [Hexagon] Fix operand swapping in HexagonPeepholeKrzysztof Parzyszek2016-04-191-2/+4
| | | | | | Also, disable zero- and size-extend optimizations for now. llvm-svn: 266821
* [Hexagon] Fix printing the address operand of S2_storerinewabsKrzysztof Parzyszek2016-04-191-9/+8
| | | | llvm-svn: 266811
* [Hexagon] Implement branch relaxationKrzysztof Parzyszek2016-04-193-0/+215
| | | | | | Patch by Sirish Pande. llvm-svn: 266792
* [NFC] Header cleanupMehdi Amini2016-04-1820-50/+16
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* Use MVT instead of EVT to remove a bunch of unnecessary calls to getSimpleVT.Craig Topper2016-04-152-8/+6
| | | | llvm-svn: 266414
* Add MachineFunctionProperty checks for AllVRegsAllocated for target passesDerek Schuff2016-04-049-2/+39
| | | | | | | | | | | | | | Summary: This adds the same checks that were added in r264593 to all target-specific passes that run after register allocation. Reviewers: qcolombet Subscribers: jyknight, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18525 llvm-svn: 265313
* Change eliminateCallFramePseudoInstr() to return an iteratorHans Wennborg2016-03-312-6/+7
| | | | | | | | | | | | | | | | | | | | | This will become necessary in a subsequent change to make this method merge adjacent stack adjustments, i.e. it might erase the previous and/or next instruction. It also greatly simplifies the calls to this function from Prolog- EpilogInserter. Previously, that had a bunch of logic to resume iteration after the call; now it just continues with the returned iterator. Note that this changes the behaviour of PEI a little. Previously, it attempted to re-visit the new instruction created by eliminateCallFramePseudoInstr(). That code was added in r36625, but I can't see any reason for it: the new instructions will obviously not be pseudo instructions, they will not have FrameIndex operands, and we have already accounted for the stack adjustment. Differential Revision: http://reviews.llvm.org/D18627 llvm-svn: 265036
* [Hexagon] Improve handling of unaligned vector loads and storesKrzysztof Parzyszek2016-03-285-56/+156
| | | | llvm-svn: 264584
* [Hexagon] Only use restore functions for single register at -OzKrzysztof Parzyszek2016-03-281-0/+11
| | | | llvm-svn: 264581
* [Hexagon] Speed up frame lowering when no optimizations are enabledKrzysztof Parzyszek2016-03-282-24/+35
| | | | | | | | - Do not optimize stack slots in optnone functions. - Get aligned-base register from HexagonMachineFunctionInfo instead of looking for ALIGNA instruction in the function's body. llvm-svn: 264580
* [Hexagon] Be sure to treat subregisters of a CSR as CSRs as wellKrzysztof Parzyszek2016-03-241-5/+8
| | | | llvm-svn: 264331
* [Hexagon] Add support for run-time stack overflow checkingKrzysztof Parzyszek2016-03-244-13/+64
| | | | | | Patch by Sundeep Kushwaha. llvm-svn: 264328
* [Hexagon] Generate PIC-specific versions of save/restore routinesKrzysztof Parzyszek2016-03-243-9/+43
| | | | | | | | | | | | In PIC mode, the registers R14, R15 and R28 are reserved for use by the PLT handling code. This causes all functions to clobber these registers. While this is not new for regular function calls, it does also apply to save/restore functions, which do not follow the standard ABI conventions with respect to the volatile/non-volatile registers. Patch by Jyotsna Verma. llvm-svn: 264324
* [Hexagon] Add handling fixups and instruction relaxationKrzysztof Parzyszek2016-03-211-112/+451
| | | | llvm-svn: 263981
* [Hexagon] Properly encode registers in duplex instructionsKrzysztof Parzyszek2016-03-213-6/+126
| | | | llvm-svn: 263980
* [Hexagon] Fix reserving emergency spill slots for register scavengerKrzysztof Parzyszek2016-03-213-35/+11
| | | | | | | - R10 and R11 are not reserved registers. - Check for reserved registers when finding unused caller-saved registers. llvm-svn: 263977
* Tweak some atomics functions in preparation for larger changes; NFC.James Y Knight2016-03-161-1/+0
| | | | | | | | | | | | | | | | - Rename getATOMIC to getSYNC, as llvm will soon be able to emit both '__sync' libcalls and '__atomic' libcalls, and this function is for the '__sync' ones. - getInsertFencesForAtomic() has been replaced with shouldInsertFencesForAtomic(Instruction), so that the decision can be made per-instruction. This functionality will be used soon. - emitLeadingFence/emitTrailingFence are no longer called if shouldInsertFencesForAtomic returns false, and thus don't need to check the condition themselves. llvm-svn: 263665
* [Hexagon] Adding missing break in switch statement. Extra operands would ↵Colin LeMahieu2016-03-161-0/+1
| | | | | | have been appended to the end. llvm-svn: 263657
* [DAG] use !isUndef() ; NFCISanjay Patel2016-03-141-1/+1
| | | | llvm-svn: 263453
* [DAG] use isUndef() ; NFCISanjay Patel2016-03-141-5/+5
| | | | llvm-svn: 263448
* [Hexagon] Fix lowering of calls with the return type of i1Krzysztof Parzyszek2016-03-041-10/+30
| | | | | | | This fixes an assertion in test/CodeGen/Hexagon/ifcvt-edge-weight.ll when run with -debug-only=isel llvm-svn: 262726
* [NFC] Convert tabs to spaces.Colin LeMahieu2016-03-011-2/+2
| | | | llvm-svn: 262411
* [Hexagon] Modifying r262258 to only be in effect in the hand assembler path, ↵Colin LeMahieu2016-03-012-14/+18
| | | | | | not the integrated assembler. llvm-svn: 262400
* TableGen: Check scheduling models for completenessMatthias Braun2016-03-013-0/+3
| | | | | | | | | | | | | | | | | | | | | | TableGen checks at compiletime that for scheduling models with "CompleteModel = 1" one of the following holds: - Is marked with the hasNoSchedulingInfo flag - The instruction is a subclass of Sched - There are InstRW definitions in the scheduling model Typical steps necessary to complete a model: - Ensure all pseudo instructions that are expanded before machine scheduling (usually everything handled with EmitYYY() functions in XXXTargetLowering). - If a CPU does not support some instructions mark the corresponding resource unsupported: "WriteRes<WriteXXX, []> { let Unsupported = 1; }". - Add missing scheduling information. Differential Revision: http://reviews.llvm.org/D17747 llvm-svn: 262384
* [Hexagon] As a size optimization, not lazy extending TPREL or DTPREL ↵Colin LeMahieu2016-02-291-8/+14
| | | | | | variants since they're usually in range. llvm-svn: 262258
* [Hexagon] Missed member initialization causing ubsan failure.Colin LeMahieu2016-02-291-1/+2
| | | | llvm-svn: 262252
* [Hexagon] Setting sign mismatch flag on expression instead of using bit tricks.Colin LeMahieu2016-02-293-16/+22
| | | | llvm-svn: 262243
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