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* Remove code copied from GenRegisterInfo.inc.Andrew Trick2013-02-222-57/+0
| | | | | | | | There's no apparent reason this code was copied from generated source into a .cpp. It sets a bad example for those working on other targets and trying to understand the register info API. llvm-svn: 175849
* Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky2013-02-214-19/+20
| | | | | | | | | | | | | | | to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. llvm-svn: 175788
* Hexagon: Expand cttz, ctlz, and ctpop for now.Anshuman Dasgupta2013-02-211-0/+5
| | | | llvm-svn: 175783
* Update TargetLowering ivars for name policy.Jim Grosbach2013-02-201-2/+2
| | | | | | | | | | | http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly ivars should be camel-case and start with an upper-case letter. A few in TargetLowering were starting with a lower-case letter. No functional change intended. llvm-svn: 175667
* Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.Jyotsna Verma2013-02-2010-32/+336
| | | | | | | | Add HexagonMCInst class which adds various Hexagon VLIW annotations. In addition, this class also includes some APIs related to the constant extenders. llvm-svn: 175634
* Hexagon: Sync TSFlags in MCTargetDesc/HexagonBaseInfo.h withJyotsna Verma2013-02-191-28/+60
| | | | | | HexagonInstrFormats.td. llvm-svn: 175537
* Hexagon: Set appropriate TSFlags to the loads/stores with global address toJyotsna Verma2013-02-151-33/+25
| | | | | | | | support constant extension. This patch doesn't introduce any functionality changes. llvm-svn: 175280
* Hexagon: Change insn class to support instruction encoding.Jyotsna Verma2013-02-145-259/+252
| | | | | | | | This patch doesn't introduce any functionality changes. It adds some new fields to the Hexagon instruction classes and changes their layout to support instruction encoding. llvm-svn: 175205
* Hexagon: Use multiclass for absolute addressing mode loads.Jyotsna Verma2013-02-141-74/+35
| | | | | | This patch doesn't introduce any functionality changes. llvm-svn: 175187
* Hexagon: add support for predicate-GPR copies.Anshuman Dasgupta2013-02-131-0/+12
| | | | llvm-svn: 175102
* Hexagon: Use absolute addressing mode loads/stores for global+offset Jyotsna Verma2013-02-136-1052/+224
| | | | | | instead of redefining separate instructions for them. llvm-svn: 175086
* MIsched: HazardRecognizers are created for each DAG. Free them.Andrew Trick2013-02-131-1/+3
| | | | llvm-svn: 175067
* Hexagon: Add support to generate predicated absolute addressing modeJyotsna Verma2013-02-121-20/+123
| | | | | | instructions. llvm-svn: 174973
* Extend Hexagon hardware loop generation to handle various additional cases:Krzysztof Parzyszek2013-02-114-382/+1470
| | | | | | | | - variety of compare instructions, - loops with no preheader, - arbitrary lower and upper bounds. llvm-svn: 174904
* Implement HexagonInstrInfo::analyzeCompare.Krzysztof Parzyszek2013-02-112-0/+86
| | | | llvm-svn: 174901
* Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handleJyotsna Verma2013-02-052-1/+214
| | | | | | zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns. llvm-svn: 174429
* Hexagon: Use multiclass for absolute addressing mode stores.Jyotsna Verma2013-02-051-102/+70
| | | | llvm-svn: 174412
* Move MRI liveouts to Hexagon return instructions.Jakob Stoklund Olesen2013-02-052-11/+10
| | | | llvm-svn: 174407
* Hexagon: Add V4 compare instructions. Enable relationship mappingJyotsna Verma2013-02-051-16/+143
| | | | | | for the existing instructions. llvm-svn: 174389
* Hexagon: Add V4 combine instructions and some more Def Pats for V2.Jyotsna Verma2013-02-043-8/+135
| | | | llvm-svn: 174331
* Replace LDriu*[bhdw]_indexed_V4 instructions with "def Pats".Jyotsna Verma2013-02-013-504/+33
| | | | llvm-svn: 174193
* Add appropriate TSFlags to the instructions that must be always extended.Jyotsna Verma2013-02-011-148/+147
| | | | llvm-svn: 174186
* [PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier2013-01-312-28/+25
| | | | | | | Each target implementation was needlessly recomputing the index. Part of rdar://13076458 llvm-svn: 174083
* Use multiclass for post-increment store instructions.Jyotsna Verma2013-01-294-346/+125
| | | | llvm-svn: 173816
* Add constant extender support for MInst type instructions.Jyotsna Verma2013-01-292-75/+151
| | | | llvm-svn: 173813
* Teach SDISel to combine fsin / fcos into a fsincos node if the followingEvan Cheng2013-01-291-0/+2
| | | | | | | | | | | | | | | | | | conditions are met: 1. They share the same operand and are in the same BB. 2. Both outputs are used. 3. The target has a native instruction that maps to ISD::FSINCOS node or the target provides a sincos library call. Implemented the generic optimization in sdisel and enabled it for Mac OSX. Also added an additional optimization for x86_64 Mac OSX by using an alternative entry point __sincos_stret which returns the two results in xmm0 / xmm1. rdar://13087969 PR13204 llvm-svn: 173755
* MIsched: Improve the interface to SchedDFS analysis (subtrees).Andrew Trick2013-01-251-1/+7
| | | | | | | Allow the strategy to select SchedDFS. Allow the results of SchedDFS to affect initialization of the scheduler state. llvm-svn: 173425
* Add indexed load/store instructions for offset validation check.Jyotsna Verma2013-01-171-0/+4
| | | | | | This patch fixes bug 14902 - http://llvm.org/bugs/show_bug.cgi?id=14902 llvm-svn: 172737
* Improve r172468: const_cast is not needed hereDmitri Gribenko2013-01-141-3/+2
| | | | llvm-svn: 172483
* Fix Another CastDavid Greene2013-01-141-1/+2
| | | | | | Properly cast code to eliminate cast-away-const errors. llvm-svn: 172468
* Remove more unnecessary # operators with nothing to paste proceeding them.Craig Topper2013-01-072-40/+40
| | | | llvm-svn: 171702
* Remove # from the beginning and end of def names. The # is a paste operator ↵Craig Topper2013-01-072-66/+66
| | | | | | and should only be used with something to paste on either side. llvm-svn: 171697
* Switch TargetTransformInfo from an immutable analysis pass that requiresChandler Carruth2013-01-072-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a TargetMachine to construct (and thus isn't always available), to an analysis group that supports layered implementations much like AliasAnalysis does. This is a pretty massive change, with a few parts that I was unable to easily separate (sorry), so I'll walk through it. The first step of this conversion was to make TargetTransformInfo an analysis group, and to sink the nonce implementations in ScalarTargetTransformInfo and VectorTargetTranformInfo into a NoTargetTransformInfo pass. This allows other passes to add a hard requirement on TTI, and assume they will always get at least on implementation. The TargetTransformInfo analysis group leverages the delegation chaining trick that AliasAnalysis uses, where the base class for the analysis group delegates to the previous analysis *pass*, allowing all but tho NoFoo analysis passes to only implement the parts of the interfaces they support. It also introduces a new trick where each pass in the group retains a pointer to the top-most pass that has been initialized. This allows passes to implement one API in terms of another API and benefit when some other pass above them in the stack has more precise results for the second API. The second step of this conversion is to create a pass that implements the TargetTransformInfo analysis using the target-independent abstractions in the code generator. This replaces the ScalarTargetTransformImpl and VectorTargetTransformImpl classes in lib/Target with a single pass in lib/CodeGen called BasicTargetTransformInfo. This class actually provides most of the TTI functionality, basing it upon the TargetLowering abstraction and other information in the target independent code generator. The third step of the conversion adds support to all TargetMachines to register custom analysis passes. This allows building those passes with access to TargetLowering or other target-specific classes, and it also allows each target to customize the set of analysis passes desired in the pass manager. The baseline LLVMTargetMachine implements this interface to add the BasicTTI pass to the pass manager, and all of the tools that want to support target-aware TTI passes call this routine on whatever target machine they end up with to add the appropriate passes. The fourth step of the conversion created target-specific TTI analysis passes for the X86 and ARM backends. These passes contain the custom logic that was previously in their extensions of the ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces. I separated them into their own file, as now all of the interface bits are private and they just expose a function to create the pass itself. Then I extended these target machines to set up a custom set of analysis passes, first adding BasicTTI as a fallback, and then adding their customized TTI implementations. The fourth step required logic that was shared between the target independent layer and the specific targets to move to a different interface, as they no longer derive from each other. As a consequence, a helper functions were added to TargetLowering representing the common logic needed both in the target implementation and the codegen implementation of the TTI pass. While technically this is the only change that could have been committed separately, it would have been a nightmare to extract. The final step of the conversion was just to delete all the old boilerplate. This got rid of the ScalarTargetTransformInfo and VectorTargetTransformInfo classes, all of the support in all of the targets for producing instances of them, and all of the support in the tools for manually constructing a pass based around them. Now that TTI is a relatively normal analysis group, two things become straightforward. First, we can sink it into lib/Analysis which is a more natural layer for it to live. Second, clients of this interface can depend on it *always* being available which will simplify their code and behavior. These (and other) simplifications will follow in subsequent commits, this one is clearly big enough. Finally, I'm very aware that much of the comments and documentation needs to be updated. As soon as I had this working, and plausibly well commented, I wanted to get it committed and in front of the build bots. I'll be doing a few passes over documentation later if it sticks. Commits to update DragonEgg and Clang will be made presently. llvm-svn: 171681
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-0215-30/+30
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Remove Function::getParamAttributes and use the AttributeSet accessor ↵Bill Wendling2012-12-301-1/+1
| | | | | | methods instead. llvm-svn: 171255
* Delete executive bit on ./lib/Target/Hexagon/HexagonAsmPrinter.h.Jakub Staszak2012-12-291-0/+0
| | | | llvm-svn: 171225
* Add constant extender support to GP-relative load/store instructions.Jyotsna Verma2012-12-202-44/+42
| | | | llvm-svn: 170672
* Add TSFlags to ALU32 type instructions for constant-extender/Relationship maps.Jyotsna Verma2012-12-203-40/+26
| | | | llvm-svn: 170671
* Rename the 'Attributes' class to 'Attribute'. It's going to represent a ↵Bill Wendling2012-12-191-1/+1
| | | | | | single attribute in the future. llvm-svn: 170502
* Use multiclass for new-value store instructions with MEMri operand.Jyotsna Verma2012-12-111-148/+46
| | | | llvm-svn: 169814
* [CMake] Update dependencies to intrinsics_gen corresponding to r169711.NAKAMURA Takumi2012-12-101-2/+2
| | | | llvm-svn: 169724
* In hexagon convertToHardwareLoop, don't deref end() iteratorMatthew Curtis2012-12-071-7/+14
| | | | | | | | | | In particular, check if MachineBasicBlock::iterator is end() before using it to call getDebugLoc(); See also this thread on llvm-commits: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121112/155914.html llvm-svn: 169634
* Define new-value store instructions with base+immediate addressing modeJyotsna Verma2012-12-051-128/+53
| | | | | | using multiclass. llvm-svn: 169432
* Use multiclass to define store instructions with base+immediate offsetJyotsna Verma2012-12-051-138/+68
| | | | | | addressing mode and immediate stored value. llvm-svn: 169408
* Fix misplaced closing brace.Matthew Curtis2012-12-051-1/+2
| | | | llvm-svn: 169404
* Define store instructions with base+register offset addressing modeJyotsna Verma2012-12-041-352/+116
| | | | | | using multiclass. llvm-svn: 169314
* Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count ↵Jyotsna Verma2012-12-043-17/+97
| | | | | | | | trailing/leading zeros) instructions. llvm-svn: 169287
* Add constant extender support to ALU32 instructions for V2.Jyotsna Verma2012-12-041-51/+79
| | | | llvm-svn: 169284
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-048-15/+15
| | | | | | | | | | missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
* Move all operand definitions into HexagonOperands.tdJyotsna Verma2012-12-042-53/+57
| | | | llvm-svn: 169213
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