summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Hexagon
Commit message (Collapse)AuthorAgeFilesLines
...
* Move generic Hexagon subtarget information into Hexagon.tdJyotsna Verma2012-12-042-64/+101
| | | | llvm-svn: 169212
* Define store instructions with base+immediate offset addressing modeJyotsna Verma2012-12-032-185/+78
| | | | | | using multiclass. llvm-svn: 169168
* Define load instructions with base+immediate offset addressing modeJyotsna Verma2012-12-031-203/+73
| | | | | | using multiclass. llvm-svn: 169153
* Define unsigned const-ext predicates.Jyotsna Verma2012-12-031-0/+128
| | | | llvm-svn: 169149
* Removing unnecessary 'else' statement from the predicates defined in ↵Jyotsna Verma2012-12-031-48/+12
| | | | | | HexagonOperards.td. llvm-svn: 169148
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-0321-118/+119
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Define signed const-ext predicates.Jyotsna Verma2012-12-031-0/+131
| | | | llvm-svn: 169117
* Use multiclass for the load instructions with MEMri operand.Jyotsna Verma2012-11-301-184/+66
| | | | llvm-svn: 169018
* Use multiclass for the store instructions with MEMri operand.Jyotsna Verma2012-11-302-163/+64
| | | | llvm-svn: 168983
* Use multiclass for the load instructions with 'base + register offset'Jyotsna Verma2012-11-301-277/+97
| | | | | | addressing mode. llvm-svn: 168976
* Use multiclass for 'transfer' instructions.Jyotsna Verma2012-11-292-80/+98
| | | | llvm-svn: 168929
* Define signed const-ext immediate operands and their predicates.Jyotsna Verma2012-11-282-0/+122
| | | | llvm-svn: 168810
* Fix comments in HexagonOperands.td.Jyotsna Verma2012-11-261-29/+27
| | | | llvm-svn: 168617
* Add new predicates for the immediate operands.Jyotsna Verma2012-11-211-4/+121
| | | | llvm-svn: 168451
* Use one common 'let' expression to set PrintMethod for all immediate operands.Jyotsna Verma2012-11-211-209/+53
| | | | llvm-svn: 168449
* Finish the renaming.Rafael Espindola2012-11-212-2/+2
| | | | llvm-svn: 168437
* Renamed HexagonImmediates.td -> HexagonOperands.td.Jyotsna Verma2012-11-212-1/+1
| | | | llvm-svn: 168434
* Removing some unused instruction definitions from the Hexagon backend.Jyotsna Verma2012-11-202-92/+0
| | | | llvm-svn: 168388
* Added multiclass for post-increment load instructions.Jyotsna Verma2012-11-144-233/+187
| | | | llvm-svn: 167974
* Test commit.Jyotsna Verma2012-11-131-0/+1
| | | | | | Add a blank line. llvm-svn: 167819
* ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.Andrew Trick2012-11-061-2/+1
| | | | | | | This is in preparation for adding "weak" DAG edges, but generally simplifies the design. llvm-svn: 167435
* Use the relationship models infrastructure to add two relations - getPredOpcodePranav Bhandarkar2012-11-013-211/+139
| | | | | | | | | | and getPredNewOpcode. The first relates non predicated instructions with their predicated forms and the second relates predicated instructions with their predicate-new forms. Patch by Jyotsna Verma! llvm-svn: 167243
* Implement a basic VectorTargetTransformInfo interface to be used by the loop ↵Nadav Rotem2012-10-241-1/+1
| | | | | | and bb vectorizers for modeling the cost of instructions. llvm-svn: 166593
* Reapply the TargerTransformInfo changes, minus the changes to LSR and ↵Nadav Rotem2012-10-182-2/+14
| | | | | | Lowerinvoke. llvm-svn: 166248
* Temporarily revert the TargetTransform changes.Bob Wilson2012-10-182-14/+2
| | | | | | | | | | | The TargetTransform changes are breaking LTO bootstraps of clang. I am working with Nadav to figure out the problem, but I am reverting it for now to get our buildbots working. This reverts svn commits: 165665 165669 165670 165786 165787 165997 and I have also reverted clang svn 165741 llvm-svn: 166168
* Add a new interface to allow IR-level passes to access codegen-specific ↵Nadav Rotem2012-10-102-2/+14
| | | | | | information. llvm-svn: 165665
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-102-30/+26
| | | | | | | | Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. llvm-svn: 165603
* Create enums for the different attributes.Bill Wendling2012-10-091-1/+1
| | | | | | | We use the enums to query whether an Attributes object has that attribute. The opaque layer is responsible for knowing where that specific attribute is stored. llvm-svn: 165488
* Move TargetData to DataLayout.Micah Villmow2012-10-086-12/+12
| | | | llvm-svn: 165402
* Use new accessor methods to query for attributes.Bill Wendling2012-10-041-1/+1
| | | | llvm-svn: 165205
* TargetLowering interface to set/get minimum block entries for jump tables.Sebastian Pop2012-09-251-0/+2
| | | | | | | | | | | | | | Provide interface in TargetLowering to set or get the minimum number of basic blocks whereby jump tables are generated for switch statements rather than an if sequence. getMinimumJumpTableEntries() defaults to 4. setMinimumJumpTableEntries() allows target configuration. This patch changes the default for the Hexagon architecture to 5 as it improves performance on some benchmarks. llvm-svn: 164628
* DAG post-process for Hexagon MI schedulerSergei Larin2012-09-142-0/+34
| | | | | | | | This patch introduces a possibility for Hexagon MI scheduler to perform some target specific post- processing on the scheduling DAG prior to scheduling. llvm-svn: 163903
* Remove redundant private field.Benjamin Kramer2012-09-142-3/+2
| | | | | | clang warned about this being unused in Release builds. llvm-svn: 163899
* Reorganize MachineScheduler interfaces and publish them in the header.Andrew Trick2012-09-112-510/+18
| | | | | | | | | | | | | | The Hexagon target decided to use a lot of functionality from the target-independent scheduler. That's fine, and other targets should be able to do the same. This reorg and API update makes that easy. For the record, ScheduleDAGMI was not meant to be subclassed. Instead, new scheduling algorithms should be able to implement MachineSchedStrategy and be done. But if need be, it's nice to be able to extend ScheduleDAGMI, so I also made that easier. The target scheduler is somewhat more apt to break that way though. llvm-svn: 163580
* Add "blocked" heuristic to the Hexagon MI scheduler.Sergei Larin2012-09-102-177/+269
| | | | | | Improve AQ instruction selection in the Hexagon MI scheduler. llvm-svn: 163523
* Fix alignment of .comm and .lcomm on mingw32.Benjamin Kramer2012-09-071-1/+1
| | | | | | | | For some reason .lcomm uses byte alignment and .comm log2 alignment so we can't use the same setting for both. Fix this by reintroducing the LCOMM enum. I verified this against mingw's gcc. llvm-svn: 163420
* MC: Overhaul handling of .lcommBenjamin Kramer2012-09-071-1/+1
| | | | | | | | | | | | | - Darwin lied about not supporting .lcomm and turned it into zerofill in the asm parser. Push the zerofill-conversion down into macho-specific code. - This makes the tri-state LCOMMType enum superfluous, there are no targets without .lcomm. - Do proper error reporting when trying to use .lcomm with alignment on a target that doesn't support it. - .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2. - Fixes PR13755 (.lcomm crashes on ELF). llvm-svn: 163395
* LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access thePranav Bhandarkar2012-09-051-0/+35
| | | | | | | | | | | | | | | subreg_hireg of register pair Rp. * lib/Target/Hexagon/HexagonPeephole.cpp(PeepholeDoubleRegsMap): New DenseMap similar to PeepholeMap that additionally records subreg info too. (runOnMachineFunction): Record information in PeepholeDoubleRegsMap and copy propagate the high sub-reg of Rp0 in Rp1 = lsr(Rp0, #32) to the instruction Rx = COPY Rp1:logreg_subreg. * test/CodeGen/Hexagon/remove_lsr.ll: New test. llvm-svn: 163214
* Remove redundant semicolons to fix -pedantic-errors build.Richard Smith2012-09-051-2/+2
| | | | llvm-svn: 163190
* Porting Hexagon MI Scheduler to the new API.Sergei Larin2012-09-048-1/+1377
| | | | | | | Change current Hexagon MI scheduler to use new converging scheduler. Integrates DFA resource model into it. llvm-svn: 163137
* Rename hasVolatileMemoryRef() to hasOrderedMemoryRef().Jakob Stoklund Olesen2012-08-291-2/+2
| | | | | | | | Ordered memory operations are more constrained than volatile loads and stores because they must be ordered with respect to all other memory operations. llvm-svn: 162861
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-221-1/+1
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
* fix HexagonSubtarget parsing of -mv flagSebastian Pop2012-08-201-17/+16
| | | | llvm-svn: 162217
* [Hexagon] Don't mark callee saved registers as clobbered by a tail callArnold Schwaighofer2012-08-131-9/+3
| | | | | | | | | | This was causing unnecessary spills/restores of callee saved registers. Fixes PR13572. Patch by Pranav Bhandarkar! llvm-svn: 161778
* Don't use getNextOperandForReg().Jakob Stoklund Olesen2012-08-081-1/+4
| | | | | | | | | This way of using getNextOperandForReg() was unlikely to work as intended. We don't give any guarantees about the order of operands in the use-def chains, so looking only at operands following a given operand in the chain doesn't make sense. llvm-svn: 161542
* default to use -mv4 when no version of Hexagon has been specifiedSebastian Pop2012-07-191-1/+5
| | | | | | | | | This fixes a bunch of make check failures of the form: Unknown Architecture Version. UNREACHABLE executed at ../lib/Target/Hexagon/HexagonSubtarget.cpp:60! llvm-svn: 160518
* Remove tabs.Bill Wendling2012-07-191-85/+85
| | | | llvm-svn: 160483
* Remove tabs.Bill Wendling2012-07-191-4/+4
| | | | llvm-svn: 160477
* Remove variable_ops from call instructions in most targets.Jakob Stoklund Olesen2012-07-133-10/+10
| | | | | | | | Call instructions are no longer required to be variadic, and variable_ops should only be used for instructions that encode a variable number of arguments, like the ARM stm/ldm instructions. llvm-svn: 160189
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-073-9/+14
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
OpenPOWER on IntegriCloud