summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Hexagon
Commit message (Collapse)AuthorAgeFilesLines
* [RDF] Correctly calculate lane masks for defsKrzysztof Parzyszek2017-04-281-2/+7
| | | | llvm-svn: 301700
* [Hexagon] Do not move a block if it is on a fall-through pathKrzysztof Parzyszek2017-04-281-3/+10
| | | | llvm-svn: 301698
* Kill off the old SimplifyInstruction API by converting remaining users.Daniel Berlin2017-04-281-3/+3
| | | | llvm-svn: 301673
* Use Argument::hasAttribute and AttributeList::ReturnIndex moreReid Kleckner2017-04-281-6/+3
| | | | | | | | | | | This eliminates many extra 'Idx' induction variables in loops over arguments in CodeGen/ and Target/. It also reduces the number of places where we assume that ReturnIndex is 0 and that we should add one to argument numbers to get the corresponding attribute list index. NFC llvm-svn: 301666
* Fix typo and place comment close to its targetKrzysztof Parzyszek2017-04-271-5/+6
| | | | | | | | Patch by Wei-Ren Chen. Differential Revision: https://reviews.llvm.org/D32594 llvm-svn: 301546
* [ValueTracking] Introduce a KnownBits struct to wrap the two APInts for ↵Craig Topper2017-04-261-4/+4
| | | | | | | | | | | | | | | | computeKnownBits This patch introduces a new KnownBits struct that wraps the two APInt used by computeKnownBits. This allows us to treat them as more of a unit. Initially I've just altered the signatures of computeKnownBits and InstCombine's simplifyDemandedBits to pass a KnownBits reference instead of two separate APInt references. I'll do similar to the SelectionDAG version of computeKnownBits/simplifyDemandedBits as a separate patch. I've added a constructor that allows initializing both APInts to the same bit width with a starting value of 0. This reduces the repeated pattern of initializing both APInts. Once place default constructed the APInts so I added a default constructor for those cases. Going forward I would like to add more methods that will work on the pairs. For example trunc, zext, and sext occur on both APInts together in several places. We should probably add a clear method that can be used to clear both pieces. Maybe a method to check for conflicting information. A method to return (Zero|One) so we don't write it out everywhere. Maybe a method for (Zero|One).isAllOnesValue() to determine if all bits are known. I'm sure there are many other methods we can come up with. Differential Revision: https://reviews.llvm.org/D32376 llvm-svn: 301432
* [Hexagon] Only increment debug counters if debug option is presentKrzysztof Parzyszek2017-04-251-6/+11
| | | | llvm-svn: 301346
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-245-34/+36
| | | | | | | | | | | | | | | 1. RegisterClass::getSize() is split into two functions: - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const; - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const; 2. RegisterClass::getAlignment() is replaced by: - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const; This will allow making those values depend on subtarget features in the future. Differential Revision: https://reviews.llvm.org/D31783 llvm-svn: 301221
* Revert "[APInt] Fix a few places that use APInt::getRawData to operate ↵Renato Golin2017-04-231-1/+1
| | | | | | | | | | | | | | | | within the normal API." This reverts commit r301105, 4, 3 and 1, as a follow up of the previous revert, which broke even more bots. For reference: Revert "[APInt] Use operator<<= where possible. NFC" Revert "[APInt] Use operator<<= instead of shl where possible. NFC" Revert "[APInt] Use ashInPlace where possible." PR32754. llvm-svn: 301111
* [APInt] Fix a few places that use APInt::getRawData to operate within the ↵Craig Topper2017-04-231-1/+1
| | | | | | | | | | normal API. getRawData exposes the internal type of the APInt class directly to its users. Ideally we wouldn't expose such an implementation detail. This patch fixes a few of the easy cases by using truncate, extract, or a rotate. llvm-svn: 301105
* [Hexagon] Generate proper offset in opt-addr-modeKrzysztof Parzyszek2017-04-192-11/+8
| | | | | | | | | Also, make a few changes to allow using the pass in .mir testcases. Among other things, change the abbreviation from opt-amode to amode-opt, because otherwise lit would expand the "opt" part to the full path to the opt binary. llvm-svn: 300707
* [Hexagon] Remove RDefMap, use Liveness:getNearestAliasedRef insteadKrzysztof Parzyszek2017-04-191-48/+5
| | | | llvm-svn: 300706
* [RDF] Switch NodeList to SmallVector from std::vectorKrzysztof Parzyszek2017-04-191-1/+2
| | | | | | | The list has a single element 75+% of the time, reservation of 4 elements is sufficient in 95% of cases. llvm-svn: 300705
* [RDF] Use faster version of findBlockKrzysztof Parzyszek2017-04-191-1/+1
| | | | llvm-svn: 300704
* [RDF] Cache register units for reg masks instead of recalculating themKrzysztof Parzyszek2017-04-192-31/+29
| | | | llvm-svn: 300702
* [Hexagon] Cache reached blocks in bit tracker instead of scanning listKrzysztof Parzyszek2017-04-192-10/+10
| | | | llvm-svn: 300701
* DAG: Make mayBeEmittedAsTailCall parameter constMatt Arsenault2017-04-182-2/+2
| | | | llvm-svn: 300603
* [RDF] No longer ignore implicit defs or uses on any instructionsKrzysztof Parzyszek2017-04-141-23/+0
| | | | | | | This used to be a Hexagon-specific treatment, but is no longer needed since it's switched to subregister liveness tracking. llvm-svn: 300369
* [RDF] Correctly enumerate reg units for reg masksKrzysztof Parzyszek2017-04-141-3/+5
| | | | llvm-svn: 300368
* [RDF] Switch RegisterAggr to a bit vector of register unitsKrzysztof Parzyszek2017-04-145-185/+168
| | | | | | | This avoids many complications related to the complex register aliasing schemes. llvm-svn: 300345
* [RDF] Refine propagation of reached uses in liveness computationKrzysztof Parzyszek2017-04-143-5/+63
| | | | llvm-svn: 300337
* [Hexagon] Fix a latent problem with interpreting live-in lane masksKrzysztof Parzyszek2017-04-141-5/+7
| | | | | | | A non-zero lane mask on a register with no subregister means that the whole register is live-in. It is equivalent to a full mask. llvm-svn: 300335
* [Hexagon] Make a couple of passes compliant with -opt-bisect-limitKrzysztof Parzyszek2017-04-142-0/+5
| | | | llvm-svn: 300329
* This patch closes PR#32216: Better testing of schedule model instruction ↵Andrew V. Tischenko2017-04-142-2/+3
| | | | | | | | latencies/throughputs. The details are here: https://reviews.llvm.org/D30941 llvm-svn: 300311
* [Hexagon] Implement HexagonTargetLowering::CanLowerReturnKrzysztof Parzyszek2017-04-132-12/+18
| | | | | | | | Patch by Michael Wu. Differential Revision: https://reviews.llvm.org/D32000 llvm-svn: 300199
* [Hexagon] Fix "LowerFormalArguments emitted a value with the wrong type!" ↵Krzysztof Parzyszek2017-04-131-1/+1
| | | | | | | | | | assertion Patch by Michael Wu. Differential Revision: https://reviews.llvm.org/D31999 llvm-svn: 300198
* Module::getOrInsertFunction is using C-style vararg instead of variadic ↵Serge Guelton2017-04-111-2/+1
| | | | | | | | | | | templates. From a user prospective, it forces the use of an annoying nullptr to mark the end of the vararg, and there's not type checking on the arguments. The variadic template is an obvious solution to both issues. Differential Revision: https://reviews.llvm.org/D31070 llvm-svn: 299949
* Revert "Turn some C-style vararg into variadic templates"Diana Picus2017-04-111-1/+2
| | | | | | | This reverts commit r299925 because it broke the buildbots. See e.g. http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15/builds/6008 llvm-svn: 299928
* Turn some C-style vararg into variadic templatesSerge Guelton2017-04-111-2/+1
| | | | | | | | | | | | Module::getOrInsertFunction is using C-style vararg instead of variadic templates. From a user prospective, it forces the use of an annoying nullptr to mark the end of the vararg, and there's not type checking on the arguments. The variadic template is an obvious solution to both issues. llvm-svn: 299925
* [Hexagon] Change the vector scaling for vector offsetsKrzysztof Parzyszek2017-04-0610-397/+456
| | | | | | | Keep full offset value on MI-level instructions, but have it scaled down in the MC-level instructions. llvm-svn: 299664
* Add MCContext argument to MCAsmBackend::applyFixup for error reportingAlex Bradbury2017-04-051-1/+2
| | | | | | | | | | | | | | | | A number of backends (AArch64, MIPS, ARM) have been using MCContext::reportError to report issues such as out-of-range fixup values in their TgtAsmBackend. This is great, but because MCContext couldn't easily be threaded through to the adjustFixupValue helper function from its usual callsite (applyFixup), these backends ended up adding an MCContext* argument and adding another call to applyFixup to processFixupValue. Adding an MCContext parameter to applyFixup makes this unnecessary, and even better - applyFixup can take a reference to MCContext rather than a potentially null pointer. Differential Revision: https://reviews.llvm.org/D30264 llvm-svn: 299529
* [Hexagon] Factor out some common code in HexagonEarlyIfConv.cpp, NFCKrzysztof Parzyszek2017-04-031-12/+10
| | | | llvm-svn: 299367
* [APInt] Move isMask and isShiftedMask out of APIntOps and into the APInt ↵Craig Topper2017-04-031-2/+2
| | | | | | | | | | class. Implement them without memory allocation for multiword This moves the isMask and isShiftedMask functions to be class methods. They now use the MathExtras.h function for single word size and leading/trailing zeros/ones or countPopulation for the multiword size. The previous implementation made multiple temorary memory allocations to do the bitwise arithmetic operations to match the MathExtras.h implementation. Differential Revision: https://reviews.llvm.org/D31565 llvm-svn: 299362
* [Hexagon] Remove unused variablesKrzysztof Parzyszek2017-03-313-18/+4
| | | | | | Found by PVS-Studio. Fixes llvm.org/PR31676. llvm-svn: 299262
* [Hexagon] Fix typo in HexagonEarlyIfCConv.cppKrzysztof Parzyszek2017-03-311-1/+1
| | | | | | Found by PVS-Studio. Fixes llvm.org/PR32480. llvm-svn: 299258
* [Hexagon] Avoid infinite loops in HexagonLoopIdiomRecognitionKrzysztof Parzyszek2017-03-231-13/+29
| | | | | | | | | - Avoid explosive growth of the simplification queue by not queuing expressions that are alredy in it. - Add an iteration counter and abort after a sufficiently large number of iterations (assuming that it's a symptom of an infinite loop). llvm-svn: 298655
* Recommit r298282 with fixes for memory allocation/deallocationKrzysztof Parzyszek2017-03-211-17/+724
| | | | | | | | | | | [Hexagon] Recognize polynomial-modulo loop idiom again Regain the ability to recognize loops calculating polynomial modulo operation. This ability has been lost due to some changes in the preceding optimizations. Add code to preprocess the IR to a form that the pattern matching code can recognize. llvm-svn: 298400
* Rename AttributeSet to AttributeListReid Kleckner2017-03-212-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This class is a list of AttributeSetNodes corresponding the function prototype of a call or function declaration. This class used to be called ParamAttrListPtr, then AttrListPtr, then AttributeSet. It is typically accessed by parameter and return value index, so "AttributeList" seems like a more intuitive name. Rename AttributeSetImpl to AttributeListImpl to follow suit. It's useful to rename this class so that we can rename AttributeSetNode to AttributeSet later. AttributeSet is the set of attributes that apply to a single function, argument, or return value. Reviewers: sanjoy, javed.absar, chandlerc, pete Reviewed By: pete Subscribers: pete, jholewinski, arsenm, dschuff, mehdi_amini, jfb, nhaehnle, sbc100, void, llvm-commits Differential Revision: https://reviews.llvm.org/D31102 llvm-svn: 298393
* Revert "[Hexagon] Recognize polynomial-modulo loop idiom again"Vitaly Buka2017-03-211-700/+17
| | | | | | | | Fix memory leaks on check-llvm tests detected by Asan. This reverts commit r298282. llvm-svn: 298329
* [Hexagon] Recognize polynomial-modulo loop idiom againKrzysztof Parzyszek2017-03-201-17/+700
| | | | | | | | | Regain the ability to recognize loops calculating polynomial modulo operation. This ability has been lost due to some changes in the preceding optimizations. Add code to preprocess the IR to a form that the pattern matching code can recognize. llvm-svn: 298282
* Make library calls sensitive to regparm module flag (Fixes PR3997).Nirav Dave2017-03-181-1/+1
| | | | | | | | | | Reviewers: mkuper, rnk Subscribers: mehdi_amini, jyknight, aemerson, llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D27050 llvm-svn: 298179
* Capitalize ArgListEntry fields. NFC.Nirav Dave2017-03-181-5/+6
| | | | llvm-svn: 298178
* [Hexagon] Updating inline saturate lanes for v62 version.Colin LeMahieu2017-03-161-1/+4
| | | | llvm-svn: 297920
* [Hexagon] Fix a condition in HexagonEarlyIfConv.cppKrzysztof Parzyszek2017-03-141-1/+1
| | | | | | This fixes llvm.org/PR32265. llvm-svn: 297745
* [RDF] Remove the map of reaching defs from copy propagationKrzysztof Parzyszek2017-03-102-57/+26
| | | | | | Use Liveness::getNearestAliasedRef to find the reaching def instead. llvm-svn: 297526
* [RDF] Implement Liveness::getNearestAliasedRef(Reg, Inst)Krzysztof Parzyszek2017-03-103-4/+66
| | | | | | | | This function will find the closest ref node aliased to Reg that is in an instruction preceding Inst. This could be used to identify the hypothetical reaching def of Reg, if Reg was a member of Inst. llvm-svn: 297524
* [Hexagon] Fixes to the bitsplit generationKrzysztof Parzyszek2017-03-091-11/+46
| | | | | | | | - Fix the insertion point, which occasionally could have been incorrect. - Avoid creating multiple bitsplits with the same operands, if an old one could be reused. llvm-svn: 297414
* [Hexagon] Refactor the DAG preprocessing code, NFCKrzysztof Parzyszek2017-03-091-32/+88
| | | | | | Extract individual transformations into their own functions. llvm-svn: 297401
* [Hexagon] Add -mhvx option to the Hexagon backendKrzysztof Parzyszek2017-03-091-2/+8
| | | | llvm-svn: 297393
* [Hexagon] Propagate zext of i1 into arithmetic code in selection DAGKrzysztof Parzyszek2017-03-091-0/+96
| | | | | | | (op ... (zext i1 c) ...) -> (select c (op ... 1 ...), (op ... 0 ...)) llvm-svn: 297391
OpenPOWER on IntegriCloud