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* [Target] dumpr() is defined only in debug builds.Davide Italiano2017-12-061-0/+2
| | | | | | This fixes the clang build on macOS. llvm-svn: 319923
* [Hexagon] Generate HVX code for vector construction and accessKrzysztof Parzyszek2017-12-068-248/+2468
| | | | | | | | | | Support for: - build vector, - extract vector element, subvector, - insert vector element, subvector, - shuffle. llvm-svn: 319901
* Modify ModRefInfo values using static inline method abstractions [NFC].Alina Sbirlea2017-12-051-1/+2
| | | | | | | | | | | | | | | | | Summary: The aim is to make ModRefInfo checks and changes more intuitive and less error prone using inline methods that abstract the bit operations. Ideally ModRefInfo would become an enum class, but that change will require a wider set of changes into FunctionModRefBehavior. Reviewers: sanjoy, george.burgess.iv, dberlin, hfinkel Subscribers: nlopes, llvm-commits Differential Revision: https://reviews.llvm.org/D40749 llvm-svn: 319821
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-0416-85/+89
| | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
* [Hexagon] Implement HexagonSubtarget::useAA()Krzysztof Parzyszek2017-11-302-1/+14
| | | | llvm-svn: 319477
* [Hexagon] Solo instructions cannot be used with new value jumpsKrzysztof Parzyszek2017-11-301-0/+3
| | | | llvm-svn: 319470
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-3011-107/+107
| | | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
* [Hexagon] Remove HexagonISD::PACKHLKrzysztof Parzyszek2017-11-293-6/+1
| | | | llvm-svn: 319352
* [Hexagon] Create helpers extractVector and insertVector in loweringKrzysztof Parzyszek2017-11-292-139/+144
| | | | llvm-svn: 319351
* [Hexagon] Use stable sort for HexagonShuffler to remove non-deterministic ↵Mandeep Singh Grang2017-11-281-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ordering Summary: This fixes failures in the following tests uncovered by D39245: LLVM :: CodeGen/Hexagon/args.ll LLVM :: CodeGen/Hexagon/constp-extract.ll LLVM :: CodeGen/Hexagon/expand-condsets-basic.ll LLVM :: CodeGen/Hexagon/gp-rel.ll LLVM :: CodeGen/Hexagon/packetize_cond_inst.ll LLVM :: CodeGen/Hexagon/simple_addend.ll LLVM :: CodeGen/Hexagon/swp-stages4.ll LLVM :: CodeGen/Hexagon/swp-vmult.ll LLVM :: CodeGen/Hexagon/swp-vsum.ll LLVM :: MC/Hexagon/align.s LLVM :: MC/Hexagon/asmMap.s LLVM :: MC/Hexagon/dis-duplex-p0.s LLVM :: MC/Hexagon/double-vector-producer.s LLVM :: MC/Hexagon/inst_select.ll LLVM :: MC/Hexagon/instructions/j.s Reviewers: colinl, kparzysz, adasgupt, slarin Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40227 llvm-svn: 319223
* [Hexagon] Make sure to zero-extend bytes before building a vectorKrzysztof Parzyszek2017-11-281-10/+12
| | | | llvm-svn: 319204
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-2812-53/+53
| | | | | | | | | | | As part of the unification of the debug format and the MIR format, always print registers as lowercase. * Only debug printing is affected. It now follows MIR. Differential Revision: https://reviews.llvm.org/D40417 llvm-svn: 319187
* Use getStoreSize() in various places instead of 'BitSize >> 3'.Jonas Paulsson2017-11-281-10/+2
| | | | | | | | | | | | | | | | | | This is needed for cases when the memory access is not as big as the width of the data type. For instance, storing i1 (1 bit) would be done in a byte (8 bits). Using 'BitSize >> 3' (or '/ 8') would e.g. give the memory access of an i1 a size of 0, which for instance makes alias analysis return NoAlias even when it shouldn't. There are no tests as this was done as a follow-up to the bugfix for the case where this was discovered (r318824). This handles more similar cases. Review: Björn Petterson https://reviews.llvm.org/D40339 llvm-svn: 319173
* [CodeGen] Rename functions PrintReg* to printReg*Francis Visoiu Mistrih2017-11-2816-55/+55
| | | | | | | | | | | LLVM Coding Standards: Function names should be verb phrases (as they represent actions), and command-like function should be imperative. The name should be camel case, and start with a lower case letter (e.g. openFile() or isFoo()). Differential Revision: https://reviews.llvm.org/D40416 llvm-svn: 319168
* [Hexagon] Implement HexagonSubtarget::isHVXVectorTypeKrzysztof Parzyszek2017-11-272-27/+14
| | | | llvm-svn: 319064
* [Hexagon] Implement buildVector32 and buildVector64 as utility functionsKrzysztof Parzyszek2017-11-222-133/+146
| | | | | | | | | Change LowerBUILD_VECTOR to use those functions. This commit will tempora- rily affect constant vector generation (it will generate constant-extended values instead of non-extended combines), but the code for the general case should be better. The constant selection part will be fixed later. llvm-svn: 318877
* [Hexagon] Add patterns to select A2_combine_ll and its variantsKrzysztof Parzyszek2017-11-221-0/+10
| | | | llvm-svn: 318876
* [Hexagon] Remove trailing spaces, NFCKrzysztof Parzyszek2017-11-222-3/+3
| | | | llvm-svn: 318875
* [Hexagon] Add HexagonSubtarget::getVectorLength()Krzysztof Parzyszek2017-11-211-0/+9
| | | | llvm-svn: 318807
* [Hexagon] Make sure that RDF does not remove EH_LABELsKrzysztof Parzyszek2017-11-211-1/+2
| | | | | | | Since EH_LABELs (and other labels) no longer have "side-effects", they should be checked for separately. llvm-svn: 318801
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-1734-48/+48
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* Add NDEBUG checks around LLVM_DUMP_METHOD functions for Wunused-function ↵Eric Christopher2017-11-161-1/+3
| | | | | | warnings. llvm-svn: 318373
* Add backend name to Target to enable runtime info to be fed back into TableGenDaniel Sanders2017-11-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | Summary: Make it possible to feed runtime information back to tablegen to enable profile-guided tablegen-eration, detection of untested tablegen definitions, etc. Being a cross-compiler by nature, LLVM will potentially collect data for multiple architectures (e.g. when running 'ninja check'). We therefore need a way for TableGen to figure out what data applies to the backend it is generating at the time. This patch achieves that by including the name of the 'def X : Target ...' for the backend in the TargetRegistry. Reviewers: qcolombet Reviewed By: qcolombet Subscribers: jholewinski, arsenm, jyknight, aditya_nandakumar, sdardis, nemanjai, ab, nhaehnle, t.p.northover, javed.absar, qcolombet, llvm-commits, fedor.sergeev Differential Revision: https://reviews.llvm.org/D39742 llvm-svn: 318352
* Recommit r317904: [Hexagon] Create HexagonISelDAGToDAG.h, NFCKrzysztof Parzyszek2017-11-102-109/+139
| | | | | | | The Windows builder did not reconstruct the HexagonGenDAGISel.inc file after the TableGen binary has changed. llvm-svn: 317921
* Revert "[Hexagon] Create HexagonISelDAGToDAG.h, NFC"Krzysztof Parzyszek2017-11-102-139/+109
| | | | | | This reverts r317904: broke Windows build. llvm-svn: 317916
* [Hexagon] Create HexagonISelDAGToDAG.h, NFCKrzysztof Parzyszek2017-11-102-109/+139
| | | | llvm-svn: 317904
* Set hasSideEffects=0 for PHI and fix affected passesAlex Bradbury2017-11-081-3/+2
| | | | | | | | | | | | | | Previously, hasSideEffects was ? for TargetOpcode::PHI and would be inferred as 1. D37065 sets the previously inferred properties explicitly. This patch sets hasSideEffects=0 for PHI, as it is for G_PHI. MachineInstr::isSafeToMove has been updated so it still returns false for PHI. Additionally, HexagonBitSimplify relied on a PHI node having the hasUnmodeledSideEffects property. This patch fixes that assumption. Differential Revision: https://reviews.llvm.org/D37097 llvm-svn: 317721
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-0810-10/+10
| | | | | | | | This header includes CodeGen headers, and is not, itself, included by any Target headers, so move it into CodeGen to match the layering of its implementation. llvm-svn: 317647
* [Hexagon] Make a test more flexible in HexagonLoopIdiomRecognitionKrzysztof Parzyszek2017-11-071-18/+51
| | | | | | | | | An "or" that sets the sign-bit can be replaced with a "xor", if the sign-bit was known to be clear before. With some changes to instruction combining, the simple sign-bit check was failing. Replace it with a more flexible one to catch more cases. llvm-svn: 317592
* Move TargetFrameLowering.h to CodeGen where it's implementedDavid Blaikie2017-11-031-1/+1
| | | | | | | | | | | This header already includes a CodeGen header and is implemented in lib/CodeGen, so move the header there to match. This fixes a link error with modular codegeneration builds - where a header and its implementation are circularly dependent and so need to be in the same library, not split between two like this. llvm-svn: 317379
* Add llvm::for_each as a range-based extensions to <algorithm> and make use ↵Aaron Ballman2017-11-031-8/+7
| | | | | | of it in some cases where it is a more clear alternative to std::for_each. llvm-svn: 317356
* [Hexagon] Prefer L2_loadrub_io over L4_loadrub_rrKrzysztof Parzyszek2017-11-021-52/+82
| | | | | | | If the offset is an immediate, avoid putting it in a register to get Rs+Rt<<#0. llvm-svn: 317275
* Fix warnings discovered by rL317076. [-Wunused-private-field]NAKAMURA Takumi2017-11-012-3/+1
| | | | llvm-svn: 317091
* Suppress a warning discovered by rL317076. [-Wunused-private-field]NAKAMURA Takumi2017-11-011-0/+1
| | | | llvm-svn: 317090
* [Hexagon] Allow the RDF optimizations to be run in .mir testcasesKrzysztof Parzyszek2017-10-302-5/+7
| | | | llvm-svn: 316904
* [Hexagon] Adjust patterns to reflect instruction selection preferencesKrzysztof Parzyszek2017-10-271-7/+30
| | | | llvm-svn: 316804
* [Hexagon] Fix an incorrect assertion in HexagonConstExtenders.cppKrzysztof Parzyszek2017-10-271-1/+1
| | | | | | | Making sure that an instruction has fewer operands than required, then attempting to access one out of range is going to fail. llvm-svn: 316785
* Hexagon: Fold a single-use textual header into its useDavid Blaikie2017-10-252-79/+56
| | | | llvm-svn: 316604
* [Hexagon] Account for negative offset when limiting max deviationKrzysztof Parzyszek2017-10-251-2/+8
| | | | | | | | | | | | | In getOffsetRange, Max can be set to 0 to force the extender replacement to be at or below the original value. This would cause the new offset to be non-negative, which is preferred for memory instructions (to reduce the likelihood of it getting constant-extended due to predication). The problem happens when the range is shifted by an offset (present in the instruction being examined) and the offset is negative. The entire range for the allowable deviation will then be strictly negative. This creates a problem, since 0 is assumed to be a valid deviation. llvm-svn: 316601
* HexagonDepTimingClasses.h: Don't mark header functions as file localDavid Blaikie2017-10-241-5/+14
| | | | llvm-svn: 316508
* [Hexagon] Return the correct chain edge for i1 function callsKrzysztof Parzyszek2017-10-231-1/+2
| | | | | | | | | | | | | | | | | In HexagonISelLowering, there is code to handle the case when a function returns an i1 type. In this case, we need to generate extra nodes to copy the result from R0 to a predicate register. The code was returning the wrong value for the chain edge which caused an assert "Wrong topological sorting" when converting the instructions to MIs. This patch fixes the problem by returning the chain for the final copy. Patch by Brendon Cahoon. llvm-svn: 316367
* [Hexagon] Add extra pattern for S4_addaddiKrzysztof Parzyszek2017-10-231-0/+2
| | | | | | One combination was missing: add(add(x,y),c). llvm-svn: 316363
* Fix MSVC 'result of 32-bit shift implicitly converted to 64 bits' warning. NFCI.Simon Pilgrim2017-10-211-2/+2
| | | | llvm-svn: 316271
* [Packetizer] Add function to check for aliasing between instructionsKrzysztof Parzyszek2017-10-201-1/+1
| | | | llvm-svn: 316243
* [Hexagon] Report error instead of crashing on wrong inline-asm constraintsKrzysztof Parzyszek2017-10-201-13/+14
| | | | llvm-svn: 316236
* [Hexagon] Reorganize and update instruction patternsKrzysztof Parzyszek2017-10-2010-2623/+2244
| | | | llvm-svn: 316228
* [Hexagon] Allow redefinition with immediates for hw loop conversionKrzysztof Parzyszek2017-10-202-7/+13
| | | | | | | | | | | Normally, if the registers holding the induction variable's bounds are redefined inside of the loop's body, the loop cannot be converted to a hardware loop. However, if the redefining instruction is actually loading an immediate value into the register, this conversion is both possible and legal (since the immediate itself will be used in the loop setup in the preheader). llvm-svn: 316218
* [Hexagon] Fix store conversion from rr to io in optimize addressing modesKrzysztof Parzyszek2017-10-191-6/+5
| | | | llvm-svn: 316170
* [Hexagon] New HVX target features.Sumanth Gundapaneni2017-10-187-86/+111
| | | | | | | | | | | | | | | | | | | | | | This patch lets the llvm tools handle the new HVX target features that are added by frontend (clang). The target-features are of the form "hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX. "hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated. The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}. Eg: "+hvxv62" For the correct HVX code generation, the user must use the following target features. For 64B mode: "+hvxv62" "+hvx-length64b" For 128B mode: "+hvxv62" "+hvx-length128b" Clang picks a default length if none is specified. If for some reason, no hvx-length is specified to llvm, the compilation will bail out. There is a corresponding clang patch. Differential Revision: https://reviews.llvm.org/D38851 llvm-svn: 316101
* [Hexagon] Update Hexagon ArchEnum and sync some downstream changes(NFC)Sumanth Gundapaneni2017-10-186-68/+76
| | | | | | Differential Revision: https://reviews.llvm.org/D38850 llvm-svn: 316099
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