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* [Hexagon] Generate valignb for shifting shuffles (instead of vdelta)Krzysztof Parzyszek2018-03-021-11/+35
| | | | llvm-svn: 326627
* [Hexagon] Handle VACOPY in isel loweringKrzysztof Parzyszek2018-03-021-0/+1
| | | | llvm-svn: 326599
* [Hexagon] Add trap1 instructionKrzysztof Parzyszek2018-03-014-0/+60
| | | | llvm-svn: 326492
* [Hexagon] Add guest registersKrzysztof Parzyszek2018-03-015-1/+234
| | | | llvm-svn: 326450
* [Hexagon] Implement target feature +reserved-r19Krzysztof Parzyszek2018-02-283-0/+8
| | | | llvm-svn: 326364
* [Hexagon] Recognize more sign-extensions as inputs to 32x32-bit multiplyKrzysztof Parzyszek2018-02-271-2/+13
| | | | llvm-svn: 326263
* [Hexagon] Add patterns for compares of i1 valuesKrzysztof Parzyszek2018-02-271-2/+4
| | | | llvm-svn: 326220
* [Hexagon] Recognize non-immediate constants in HexagonConstPropagationKrzysztof Parzyszek2018-02-232-6/+11
| | | | llvm-svn: 325954
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-232-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
* [DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner.Amaury Sechet2018-02-231-0/+2
| | | | | | | | | | | | | | | Summary: There are transformation that change setcc into other constructs, and transform that try to reconstruct a setcc from the brcond condition. Depending on what order these transform are done, the end result differs. Most of the time, it is preferable to get a setcc as a brcond argument (and this is why brcond try to recreate the setcc in the first place) so we ensure this is done every time by also doing it at the setcc level when the only user is a brcond. Reviewers: spatel, hfinkel, niravd, craig.topper Subscribers: nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D41235 llvm-svn: 325892
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-02-221-1/+1
| | | | | | "a a" -> "a" llvm-svn: 325752
* [Hexagon] Add TargetRegisterInfo::getPointerRegClass() overrideTobias Edler von Koch2018-02-212-0/+9
| | | | llvm-svn: 325731
* [Hexagon] Return true in enableMultipleCopyHints().Jonas Paulsson2018-02-211-0/+2
| | | | | | | | | | Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Krzysztof Parzyszek llvm-svn: 325697
* [Hexagon] Handle *Low8 register classes in early if-conversionKrzysztof Parzyszek2018-02-201-0/+2
| | | | llvm-svn: 325606
* [Hexagon] Fix alignment calculation of stack objects in Hexagon bit trackerKrzysztof Parzyszek2018-02-203-6/+6
| | | | llvm-svn: 325580
* Recommit [Hexagon] Make the vararg handling a bit more robustKrzysztof Parzyszek2018-02-151-19/+11
| | | | | | | Use the FunctionType of the callee when it's available. It may not be available for synthetic calls to functions specified by external symbols. llvm-svn: 325269
* Revert "[Hexagon] Make the vararg handling a bit more robust"Krzysztof Parzyszek2018-02-151-8/+19
| | | | | | This is breaking lit tests. llvm-svn: 325266
* [Hexagon] Make the vararg handling a bit more robustKrzysztof Parzyszek2018-02-151-19/+8
| | | | | | | The FunctionType of the callee is always available, even if the Function of the callee is not. Use that to get the number of fixed parameters. llvm-svn: 325259
* [Hexagon] Fix lowering of formal arguments after r324737Krzysztof Parzyszek2018-02-151-18/+16
| | | | | | Lowering of formal arguments needs to be aware of vararg functions. llvm-svn: 325255
* [Hexagon] Split HVX vector pair loads/stores, expand unaligned loadsKrzysztof Parzyszek2018-02-145-85/+222
| | | | llvm-svn: 325169
* [Hexagon] Simplify some code, NFCKrzysztof Parzyszek2018-02-131-114/+44
| | | | llvm-svn: 325014
* [Hexagon] Remove unnecessary checkKrzysztof Parzyszek2018-02-131-2/+0
| | | | llvm-svn: 325013
* [CodeGen] Add a -trap-unreachable option for debuggingDavid Green2018-02-121-6/+0
| | | | | | | | | | | Add a common -trap-unreachable option, similar to the target specific hexagon equivalent, which has been replaced. This turns unreachable instructions into traps, which is useful for debugging. Differential Revision: https://reviews.llvm.org/D42965 llvm-svn: 324880
* [Hexagon] Update uses of deprecated IRBuilder CreateMemCpy/Move callsDaniel Neilson2018-02-091-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change is part of step five in the series of changes to remove alignment argument from memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the Hexagon LoopIdiom pass to cease using the old IRBuilder createMemCpy/createMemMove single-alignment APIs in favour of the new API that allows setting source and destination alignments independently. Steps: Step 1) Remove alignment parameter and create alignment parameter attributes for memcpy/memmove/memset. ( rL322965, rC322964, rL322963 ) Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing source and dest alignments. ( rL323597 ) Step 3) Update Clang to use the new IRBuilder API. ( rC323617 ) Step 4) Update Polly to use the new IRBuilder API. ( rL323618 ) Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API, and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment() and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278, rL324384, rL324395, rL324402, rL324626, rL324642, rL324653, rL324654, rL324773, rL324774, rL324781 ) Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the MemIntrinsicInst::[get|set]Alignment() methods. Reference http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html llvm-svn: 324784
* [Hexagon] Add code to select QTRUE and QFALSEKrzysztof Parzyszek2018-02-093-0/+29
| | | | | | Fixes http://llvm.org/PR36320. llvm-svn: 324763
* [Hexagon] Express calling conventions via .td file instead of hand-codingKrzysztof Parzyszek2018-02-094-531/+255
| | | | | | Additionally, simplify the rest of the argument/parameter lowering code. llvm-svn: 324737
* [Hexagon] Extract HVX lowering and selection into HVX-specific files, NFCKrzysztof Parzyszek2018-02-066-581/+572
| | | | llvm-svn: 324392
* [Hexagon] Lower concat of more than 2 vectors into build_vectorKrzysztof Parzyszek2018-02-062-15/+24
| | | | llvm-svn: 324391
* [Hexagon] Don't form new-value jumps from floating-point instructionsKrzysztof Parzyszek2018-02-061-0/+16
| | | | | | | Additionally, verify that the register defined by the producer is a 32-bit register. llvm-svn: 324381
* [Hexagon] Remove leftover assertKrzysztof Parzyszek2018-02-061-3/+1
| | | | llvm-svn: 324352
* [Hexagon] Split HVX operations on vector pairsKrzysztof Parzyszek2018-02-064-70/+265
| | | | | | | | Vector pairs are legal types, but not every operation can work on pairs. For those operations that are legal for single vectors, generate a concat of their results on pair halves. llvm-svn: 324350
* [Hexagon] Add helper functions to identify single/pair vector types, NFCKrzysztof Parzyszek2018-02-062-3/+17
| | | | llvm-svn: 324349
* [Hexagon] Handle lowering of SETCC via setCondCodeActionKrzysztof Parzyszek2018-02-064-72/+82
| | | | | | | | | | It was expanded directly into instructions earlier. That was to avoid loads from a constant pool for a vector negation: "xor x, splat(i1 -1)". Implement ISD opcodes QTRUE and QFALSE to denote logical vectors of all true and all false values, and handle setcc with negations through selection patterns. llvm-svn: 324348
* [Hexagon] Memoize instruction positions in BitTrackerKrzysztof Parzyszek2018-02-052-10/+22
| | | | llvm-svn: 324250
* BitTracker.h needs a full definition of MachineInstr, so include the ↵Benjamin Kramer2018-02-051-1/+1
| | | | | | | | | | defining file. Patch by Dean Sturtevant! Differential Revision: https://reviews.llvm.org/D42907 llvm-svn: 324245
* [Hexagon] Forgot about HexagonISD::VZERO in selecting const vectorsKrzysztof Parzyszek2018-02-051-1/+1
| | | | llvm-svn: 324244
* [Hexagon] Don't use garbage mask in HvxSelector::shuffp2Krzysztof Parzyszek2018-02-051-0/+2
| | | | | | | | The function shuffp2 was breaking up a wide shuffle into a pair of narrower ones, except that the narrower shuffle masks were actually uninitialized. llvm-svn: 324243
* [Hexagon] Use V6_vmpyih for halfword multiplicationKrzysztof Parzyszek2018-02-051-5/+6
| | | | | | | Unlike V6_vmpyhv, it produces the result in the exact form that is expected without the need for a shuffle. llvm-svn: 324241
* [Hexagon] Rename HexagonISelLowering::getNode to getInstr, NFCKrzysztof Parzyszek2018-01-313-56/+56
| | | | llvm-svn: 323916
* [Hexagon] Implement HVX codegen for vector shiftsKrzysztof Parzyszek2018-01-314-67/+54
| | | | llvm-svn: 323914
* [Hexagon] Handle ANY_EXTEND_VECTOR_INREG in loweringKrzysztof Parzyszek2018-01-311-0/+4
| | | | llvm-svn: 323912
* [Hexagon] Handle SETCC on vector pairs in loweringKrzysztof Parzyszek2018-01-312-1/+16
| | | | llvm-svn: 323911
* [Hexagon] Handle BUILD_VECTOR from undef values in buildHvxVectorRegKrzysztof Parzyszek2018-01-311-1/+4
| | | | llvm-svn: 323889
* [Hexagon] Only process bitcasts of vsplats when selecting const vectorsKrzysztof Parzyszek2018-01-311-1/+6
| | | | | | | | Selecting of constant HVX vectors involves some "manual processing", which mishandled an unrelated BITCAST operation causing a selection error. llvm-svn: 323887
* [RDF] Clear the renamable flag when copy propagating reserved registersKrzysztof Parzyszek2018-01-301-2/+6
| | | | llvm-svn: 323831
* [Hexagon] Handle truncates in polynomial multiply idiom recognitionKrzysztof Parzyszek2018-01-301-12/+70
| | | | | | | This is in anticipation of https://reviews.llvm.org/D42424, which would otherwise break one of the pmpy testcases. llvm-svn: 323824
* [Hexagon] Handle non-aligned offsets in globals in extender optimizationKrzysztof Parzyszek2018-01-301-18/+52
| | | | | | | | | | Instructions like memd(r0+##global+1) are legal as long as the entire address is properly aligned. Assuming that "global" is aligned at an 8-byte boundary, the expression "global+1" appears to be misaligned. Handle such cases in HexagonConstExtenders, and make sure that any non- extended offsets generated are still aligned accordingly. llvm-svn: 323799
* Revert: [Hexagon] Make sure that offset on globals matches alignment ↵Krzysztof Parzyszek2018-01-302-41/+14
| | | | | | | | | | | | | requirements This reverts r323562, since it wasn't actually necessary. Constant- extended offsets do not need to be aligned, as long as the effective address is aligned. Keep the testcase, with a modification which checks that such offsets are not unnecessarily avoided. llvm-svn: 323798
* Inline variable only used within assert.Richard Trieu2018-01-261-2/+1
| | | | llvm-svn: 323569
* [Hexagon] Generate constant splats instead of loads from constant poolKrzysztof Parzyszek2018-01-263-27/+55
| | | | llvm-svn: 323568
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