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* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-144-11/+11
| | | | | | size. llvm-svn: 186274
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-041-5/+0
| | | | | | These exception-related opcodes are not used any longer. llvm-svn: 185625
* Revert r185595-185596 which broke buildbots.Jakob Stoklund Olesen2013-07-041-0/+5
| | | | | | | Revert "Simplify landing pad lowering." Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes." llvm-svn: 185600
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-031-5/+0
| | | | | | These exception-related opcodes are not used any longer. llvm-svn: 185596
* Hexagon: Avoid unused variable warnings in Release builds.Benjamin Kramer2013-07-021-6/+2
| | | | llvm-svn: 185445
* Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ...Richard Trieu2013-07-011-7/+5
| | | | llvm-svn: 185392
* Change assert(0 && "text") to llvm_unreachable(0 && "text")Richard Trieu2013-06-281-2/+2
| | | | llvm-svn: 185243
* Fix broken asserts that never fire.Richard Trieu2013-06-281-2/+2
| | | | | | | | Change assert("text") to assert(0 && "text"). The first case is a const char * to bool conversion, which always evaluates to true, never triggering the assert. The second case will always trigger the assert. llvm-svn: 185227
* The getRegForInlineAsmConstraint function should only accept MVT value types.Chad Rosier2013-06-222-3/+3
| | | | llvm-svn: 184642
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-193-12/+12
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184360
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE ↵David Blaikie2013-06-162-15/+0
| | | | | | | | | | MachineInstrs Frame index handling is now target-agnostic, so delete the target hooks for creation & asm printing of target-specific addressing in DBG_VALUEs and any related functions. llvm-svn: 184067
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-151-2/+2
| | | | | | | | | | | | | Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. llvm-svn: 184032
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-079-19/+25
| | | | | | the internals of TargetMachine could change. llvm-svn: 183490
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-061-2/+2
| | | | | | | Caching it as a pointer allows us to reset it if the TargetMachine object changes. llvm-svn: 183361
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-311-2/+2
| | | | | | | This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. llvm-svn: 183061
* Order CALLSEQ_START and CALLSEQ_END nodes.Andrew Trick2013-05-291-2/+3
| | | | | | | | | | | | Fixes PR16146: gdb.base__call-ar-st.exp fails after pre-RA-sched=source fixes. Patch by Xiaoyi Guo! This also fixes an unsupported dbg.value test case. Codegen was previously incorrect but the test was passing by luck. llvm-svn: 182885
* Hexagon: Typo fix.Jyotsna Verma2013-05-281-5/+5
| | | | llvm-svn: 182790
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-255-45/+45
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* Hexagon: Make helper functions static.Benjamin Kramer2013-05-232-3/+5
| | | | llvm-svn: 182588
* Hexagon: SelectionDAG should not use MVT::Other to check the legality of BR_CC.Jyotsna Verma2013-05-211-1/+0
| | | | llvm-svn: 182390
* Add LLVMContext argument to getSetCCResultTypeMatt Arsenault2013-05-181-1/+1
| | | | llvm-svn: 182180
* Don't cast away constness.Benjamin Kramer2013-05-171-2/+2
| | | | llvm-svn: 182086
* Remove dead calls to addFrameMove.Rafael Espindola2013-05-161-25/+0
| | | | | | Without a PROLOG_LABEL present, the cfi instructions are never printed. llvm-svn: 182016
* Hexagon: Pass to replace tranfer/copy instructions into combine instructionJyotsna Verma2013-05-145-0/+686
| | | | | | where possible. llvm-svn: 181817
* Hexagon: Add patterns to generate 'combine' instructions.Jyotsna Verma2013-05-141-0/+87
| | | | llvm-svn: 181805
* Hexagon: ArePredicatesComplement should not restrict itself to TFRs.Jyotsna Verma2013-05-141-5/+31
| | | | llvm-svn: 181803
* Hexagon: Remove dead-code after unconditional return from addPreSched2.Jyotsna Verma2013-05-141-3/+0
| | | | llvm-svn: 181797
* Suppress GCC compiler warnings in release builds about variables that are onlyDuncan Sands2013-05-131-0/+1
| | | | | | read in asserts. llvm-svn: 181689
* Remove the MachineMove class.Rafael Espindola2013-05-132-4/+6
| | | | | | | | | | | | It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. llvm-svn: 181680
* Change getFrameMoves to return a const reference.Rafael Espindola2013-05-111-5/+3
| | | | | | | To add a frame now there is a dedicated addFrameMove which also takes care of constructing the move itself. llvm-svn: 181657
* Fix unused variable error.Jyotsna Verma2013-05-101-2/+1
| | | | | | | Earlier, this variable was used in an assert and was causing failure on darwin. llvm-svn: 181630
* Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore.Jyotsna Verma2013-05-104-707/+81
| | | | | | No functionality change. llvm-svn: 181628
* Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.Jyotsna Verma2013-05-108-703/+170
| | | | llvm-svn: 181624
* Remove unused argument.Rafael Espindola2013-05-103-6/+4
| | | | llvm-svn: 181618
* Remove unused function.Rafael Espindola2013-05-102-11/+0
| | | | llvm-svn: 181606
* Hexagon: Remove switch cases from GetDotNewPredOp and isPostIncrement functions.Jyotsna Verma2013-05-093-593/+46
| | | | | | No functionality change. llvm-svn: 181535
* Hexagon: Use relation map for getMatchingCondBranchOpcode() and Jyotsna Verma2013-05-091-535/+5
| | | | | | getInvertedPredicatedOpcode() functions instead of switch cases. llvm-svn: 181530
* Hexagon: Fix Small Data support to handle -G 0 correctly.Jyotsna Verma2013-05-077-2/+199
| | | | llvm-svn: 181344
* Reverting r181331.Jyotsna Verma2013-05-076-196/+3
| | | | | | Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt. llvm-svn: 181334
* Hexagon: Fix Small Data support to handle -G 0 correctly.Jyotsna Verma2013-05-076-3/+196
| | | | llvm-svn: 181331
* Hexagon: Set accessSize and addrMode on all load/store instructions.Jyotsna Verma2013-05-074-68/+125
| | | | llvm-svn: 181324
* Print IR from Hexagon MI passes with -print-before/after-all.Krzysztof Parzyszek2013-05-066-17/+79
| | | | llvm-svn: 181255
* Cleanup of the HexagonTargetMachine setup.Krzysztof Parzyszek2013-05-061-29/+34
| | | | llvm-svn: 181250
* Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.Jyotsna Verma2013-05-066-407/+307
| | | | llvm-svn: 181235
* Make references to HexagonTargetMachine "const".Krzysztof Parzyszek2013-05-066-25/+26
| | | | llvm-svn: 181233
* Use consistent function names.Krzysztof Parzyszek2013-05-043-3/+3
| | | | llvm-svn: 181090
* Fix missing include in Hexagon code for Release+AssertsReid Kleckner2013-05-031-0/+1
| | | | llvm-svn: 180983
* reverting r180953Jyotsna Verma2013-05-025-305/+404
| | | | llvm-svn: 180964
* Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.Jyotsna Verma2013-05-025-404/+305
| | | | llvm-svn: 180953
* Hexagon - Add peephole optimizations for zero extends.Pranav Bhandarkar2013-05-022-0/+40
| | | | | | | | | | | | * lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a sequence of a pair of i32->i64 extensions followed by a "bitwise or" into COMBINE_rr. * lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg. * test/CodeGen/Hexagon/union-1.ll: New test. * test/CodeGen/Hexagon/combine_ir.ll: Fix test. llvm-svn: 180946
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