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* [Hexagon] Use correct offset when extracting from the high wordKrzysztof Parzyszek2017-03-081-0/+1
| | | | | | | | When extracting a bitfield from the high register in a register pair, the final offset should be relative to the high register (for 32-bit extracts). llvm-svn: 297288
* [Hexagon] Check for presence before looking registers up in bit trackerKrzysztof Parzyszek2017-03-071-0/+4
| | | | llvm-svn: 297240
* [Hexagon] Generate bitsplit instructionKrzysztof Parzyszek2017-03-071-1/+118
| | | | llvm-svn: 297239
* [Hexagon] Do not insert instructions before PHI nodesKrzysztof Parzyszek2017-03-071-1/+3
| | | | llvm-svn: 297141
* [Hexagon] Early-if-convert branches that may exit the loopKrzysztof Parzyszek2017-03-061-63/+106
| | | | | | | | | | | | | | | | Merge the tail block into the loop in cases where the main loop body exits early, subject to profitability constraints. This will coalesce the loop body into fewer blocks. For example: loop: loop: // loop body // loop body if (...) jump exit --> // more body more: if (...) jump exit // more body jump loop jump loop llvm-svn: 297033
* [Hexagon] Mark dead defs as <dead> in expand-condsetsKrzysztof Parzyszek2017-03-061-12/+28
| | | | | | | | | The code in updateDeadFlags removed unnecessary <dead> flags, but there can be cases where such a flag is not set, and yet a register has become dead. For example, if a mux with identical inputs is replaced with a COPY, the predicate register may no longer be used after that. llvm-svn: 297032
* [Hexagon] Pick a dot-old instruction that matches the architectureKrzysztof Parzyszek2017-03-063-4/+25
| | | | llvm-svn: 297031
* Make TargetInstrInfo::isPredicable take a const reference, NFCKrzysztof Parzyszek2017-03-032-2/+2
| | | | llvm-svn: 296901
* [Hexagon] Pick the right branch opcode depending on branch probabilitiesKrzysztof Parzyszek2017-03-021-15/+69
| | | | | | | Specifically, pick the opcode with the correct branch prediction, i.e. jump:t or jump:nt. llvm-svn: 296821
* [Hexagon] Skip blocks that define vector predicate registers in early-ifKrzysztof Parzyszek2017-03-021-2/+8
| | | | llvm-svn: 296777
* [Hexagon] Properly handle 'q' constraint in 128-byte vector modeKrzysztof Parzyszek2017-03-021-22/+10
| | | | llvm-svn: 296772
* [RDF] Replace {} with explicit constructor, since not all compilers like itKrzysztof Parzyszek2017-03-011-1/+1
| | | | llvm-svn: 296666
* [RDF] Add recursion limit to getAllReachingDefsRecKrzysztof Parzyszek2017-03-013-9/+40
| | | | | | | For large programs this function can take significant amounts of time. Let it abort gracefully when the program is too complex. llvm-svn: 296662
* [Hexagon] Fix lowering of formal arguments of type i1Krzysztof Parzyszek2017-03-011-3/+20
| | | | | | | | | | | On Hexagon, values of type i1 are passed in registers of type i32, even though i1 is not a legal value for these registers. This is a special case and needs special handling to maintain consistency of the lowering information. This fixes PR32089. llvm-svn: 296645
* [Hexagon] Generate extract instructions more aggressivelyKrzysztof Parzyszek2017-02-281-1/+201
| | | | llvm-svn: 296537
* [Hexagon] Fix instruction selection for sign-extending i1 to i64Krzysztof Parzyszek2017-02-281-27/+28
| | | | llvm-svn: 296532
* [Hexagon] Defs and clobbers can overlapKrzysztof Parzyszek2017-02-271-5/+4
| | | | llvm-svn: 296365
* [Hexagon] Undo shift folding where it could simplify addressing modeKrzysztof Parzyszek2017-02-241-3/+75
| | | | | | | | | | | | For example, avoid (single shift): r0 = and(##536870908,lsr(r0,#3)) r0 = memw(r1+r0<<#0) in favor of (two shifts): r0 = lsr(r0,#5) r0 = memw(r1+r0<<#2) llvm-svn: 296196
* [Hexagon] Prettify code in HexagonDAGToDAGISel::SelectKrzysztof Parzyszek2017-02-241-47/+13
| | | | llvm-svn: 296187
* [Hexagon] Handle saturations in Hexagon bit trackerKrzysztof Parzyszek2017-02-231-0/+14
| | | | llvm-svn: 296026
* [Hexagon] Allow setting register in BitVal without storing into mapKrzysztof Parzyszek2017-02-232-6/+13
| | | | | | | | | | | In the bit tracker, references to other bit values in which the register is 0 are prohibited. This means that generating self-referential register cells like { w:32 [0-15]:s[0-15] [16-31]:s[15] } is impossible. In order to get a self-referential cell, it had to be stored into a map and then reloaded from it. To avoid this step, add a function that will set the register to a given value without going through the map. llvm-svn: 296025
* [Hexagon] Avoid IMPLICIT_DEFs as new-value producersKrzysztof Parzyszek2017-02-231-0/+2
| | | | llvm-svn: 295997
* [Hexagon] Patterns for CTPOP, BSWAP and BITREVERSEKrzysztof Parzyszek2017-02-233-23/+16
| | | | llvm-svn: 295981
* [Hexagon] Implement @llvm.readcyclecounter()Krzysztof Parzyszek2017-02-226-9/+34
| | | | llvm-svn: 295892
* [RDF] Support for partial structural aliases in RegisterAggrKrzysztof Parzyszek2017-02-222-61/+67
| | | | llvm-svn: 295883
* [Hexagon] Add intrinsics for masked vector storesKrzysztof Parzyszek2017-02-221-0/+19
| | | | | | Patch by Harsha Jagasia. llvm-svn: 295879
* [RDF] Skip undef uses when calculating kill flagsKrzysztof Parzyszek2017-02-221-1/+1
| | | | llvm-svn: 295856
* [RDF] Only access block live-ins when tracking livenessKrzysztof Parzyszek2017-02-221-2/+4
| | | | llvm-svn: 295855
* Fix 'variable set but not used' warning when assertions are disabled.Simon Pilgrim2017-02-191-0/+2
| | | | llvm-svn: 295585
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-1718-116/+271
| | | | | | Reapply r295371 with a fix for the Windows bot failures. llvm-svn: 295504
* Revert "[Hexagon] Start using regmasks on calls"Rafael Espindola2017-02-1718-270/+115
| | | | | | | | | | This reverts commit r295371. It broke windows bots: http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio llvm-svn: 295402
* Fix -Wunused-lambda-capture by removing some unused lambda capturesDavid Blaikie2017-02-161-2/+2
| | | | llvm-svn: 295373
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-1618-115/+270
| | | | | | All the cool targets are doing it... llvm-svn: 295371
* [RDF] Aggregate shadow phi uses into one cluster when propagating live infoKrzysztof Parzyszek2017-02-162-70/+68
| | | | llvm-svn: 295366
* [RDF] Differentiate between defining and clobbering nodesKrzysztof Parzyszek2017-02-164-13/+88
| | | | | | | | | | Defining nodes should not alias with one another, while clobbering nodes can. When pushing defs on stacks, push clobbers first, link non-clobbering defs, then push the defs. The data flow in a statement is now: uses -> clobbers -> defs. llvm-svn: 295356
* [RDF] Move normalize(RegisterRef) to PhysicalRegisterInfoKrzysztof Parzyszek2017-02-166-45/+36
| | | | | | Remove the duplicate from DFG and make some members of PRI private. llvm-svn: 295351
* [Hexagon] Remove leftover debugging codeKrzysztof Parzyszek2017-02-141-4/+0
| | | | llvm-svn: 295078
* Fix "left shift of negative value -1" introduced by r294805Vitaly Buka2017-02-111-1/+1
| | | | llvm-svn: 294843
* Move symbols from the global namespace into (anonymous) namespaces. NFC.Benjamin Kramer2017-02-112-5/+3
| | | | llvm-svn: 294837
* [Hexagon] Introduce Hexagon V62Krzysztof Parzyszek2017-02-1018-61/+4032
| | | | llvm-svn: 294805
* [Hexagon] Remove unused .td filesKrzysztof Parzyszek2017-02-107-2572/+0
| | | | llvm-svn: 294775
* [Hexagon] Replace instruction definitions with auto-generated onesKrzysztof Parzyszek2017-02-1037-12829/+48409
| | | | llvm-svn: 294753
* Drop graph_ prefixDaniel Berlin2017-02-094-7/+7
| | | | llvm-svn: 294621
* GraphTraits: Add range versions of graph traits functions (graph_nodes, ↵Daniel Berlin2017-02-094-32/+17
| | | | | | | | | | | | | | | | | | | | | | | | | graph_children, inverse_graph_nodes, inverse_graph_children). Summary: Convert all obvious node_begin/node_end and child_begin/child_end pairs to range based for. Sending for review in case someone has a good idea how to make graph_children able to be inferred. It looks like it would require changing GraphTraits to be two argument or something. I presume inference does not happen because it would have to check every GraphTraits in the world to see if the noderef types matched. Note: This change was 3-staged with clang as well, which uses Dominators/etc from LLVM. Reviewers: chandlerc, tstellarAMD, dblaikie, rsmith Subscribers: arsenm, llvm-commits, nhaehnle Differential Revision: https://reviews.llvm.org/D29767 llvm-svn: 294620
* [Hexagon] Fix decoding conflict between A2_zxtb and A4_extKrzysztof Parzyszek2017-02-082-1/+3
| | | | llvm-svn: 294472
* [Hexagon] Update instruction typesKrzysztof Parzyszek2017-02-077-31/+77
| | | | | | | | | Remove TypeXTYPE, TypeALU32, TypeSYSTEM, TypeJR, and instead use their architecture counterparts. Patch by Colin LeMahieu. llvm-svn: 294321
* [Hexagon] Remove encoding bits from mapped instructionsKrzysztof Parzyszek2017-02-074-18/+48
| | | | | | | | | | - Map A2_zxtb to A2_andir. - Map PS_call_nr J2_call. - Map A2_tfr[t|f][new] to A2_padd[t|f][new]. Patch by Colin LeMahieu. llvm-svn: 294320
* [Hexagon] Address ASAN and UBSAN failures after r294226Krzysztof Parzyszek2017-02-074-16/+18
| | | | | | Reinstate r294256 with a fix. llvm-svn: 294269
* Revert "[Hexagon] Address ASAN and UBSAN failures after r294226"Krzysztof Parzyszek2017-02-063-15/+13
| | | | | | | This reverts commit r294256. It seems to be causing more problems instead of solving them. llvm-svn: 294259
* [Hexagon] Adding gp+ to the syntax of gp-relative instructionsKrzysztof Parzyszek2017-02-062-9/+65
| | | | | | Patch by Colin LeMahieu. llvm-svn: 294258
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