| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [MachineOperand][Target] MachineOperand::isRenamable semantics changes | Geoff Berry | 2018-02-23 | 1 | -3/+0 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931 | ||||
| * | [RDF] Clear the renamable flag when copy propagating reserved registers | Krzysztof Parzyszek | 2018-01-30 | 1 | -2/+6 |
| | | | | | llvm-svn: 323831 | ||||
| * | Fix a bunch more layering of CodeGen headers that are in Target | David Blaikie | 2017-11-17 | 1 | -2/+2 |
| | | | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490 | ||||
| * | [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use ↵ | Eugene Zelenko | 2017-08-01 | 1 | -9/+14 |
| | | | | | | | warnings; other minor fixes (NFC). llvm-svn: 309746 | ||||
| * | [RDF] Use faster version of findBlock | Krzysztof Parzyszek | 2017-04-19 | 1 | -1/+1 |
| | | | | | llvm-svn: 300704 | ||||
| * | [RDF] Remove the map of reaching defs from copy propagation | Krzysztof Parzyszek | 2017-03-10 | 1 | -52/+20 |
| | | | | | | | Use Liveness::getNearestAliasedRef to find the reaching def instead. llvm-svn: 297526 | ||||
| * | [RDF] Differentiate between defining and clobbering nodes | Krzysztof Parzyszek | 2017-02-16 | 1 | -1/+1 |
| | | | | | | | | | | | Defining nodes should not alias with one another, while clobbering nodes can. When pushing defs on stacks, push clobbers first, link non-clobbering defs, then push the defs. The data flow in a statement is now: uses -> clobbers -> defs. llvm-svn: 295356 | ||||
| * | [RDF] Switch RegisterRef to be a pair (Register, LaneMask) | Krzysztof Parzyszek | 2016-10-14 | 1 | -38/+27 |
| | | | | | | | | | | Use PackedRegisterRef to store the register information in the graph nodes. This commit also removes support for virtual registers. It has never been tested or used. It will be possible to add it back if there is a need. llvm-svn: 284255 | ||||
| * | [RDF] Replace RegisterAliasInfo with target-independent code using lane masks | Krzysztof Parzyszek | 2016-10-03 | 1 | -2/+2 |
| | | | | | llvm-svn: 283122 | ||||
| * | [hexagon] Move BlockRanges and RDF stuff into the llvm namespace. | Benjamin Kramer | 2016-05-27 | 1 | -3/+2 |
| | | | | | | | No functional change intended. llvm-svn: 270980 | ||||
| * | [RDF] Handle undefined registers in RDF copy propagation | Krzysztof Parzyszek | 2016-04-28 | 1 | -1/+6 |
| | | | | | | | | When updating the graph, make sure that new uses without reaching defs are handled correctly. llvm-svn: 267891 | ||||
| * | [RDF] Improvements to copy propagation | Krzysztof Parzyszek | 2016-01-18 | 1 | -71/+138 |
| | | | | | | | | - Allow any instruction to define equality between registers. - Keep the DFG updated. llvm-svn: 258075 | ||||
| * | RDF: Copy propagation | Krzysztof Parzyszek | 2016-01-12 | 1 | -0/+180 |
| This is a very limited implementation of DFG-based copy propagation. It only handles actual COPY instructions (does not handle other equivalents such as add-immediate with a 0 operand). The major limitation is that it does not update the DFG: that will be the change required to make it more robust (hopefully coming up soon). llvm-svn: 257490 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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