bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	[Hexagon] Missed member initialization causing ubsan failure.	Colin LeMahieu	2016-02-29	1	-1/+2
\| \| \| \|	llvm-svn: 262252
*	[Hexagon] Setting sign mismatch flag on expression instead of using bit tricks.	Colin LeMahieu	2016-02-29	1	-0/+8
\| \| \| \|	llvm-svn: 262243
*	[Hexagon] Adding relocation for code size, cold path optimization allowing a ↵	Colin LeMahieu	2016-02-16	1	-1/+6
\| \| \| \| \| \| \| \| \| \| \| \|	23-bit 4-byte aligned relocation to be a valid instruction encoding. The usual way to get a 32-bit relocation is to use a constant extender which doubles the size of the instruction, 4 bytes to 8 bytes. Another way is to put a .word32 and mix code and data within a function. The disadvantage is it's not a valid instruction encoding and jumping over it causes prefetch stalls inside the hardware. This relocation packs a 23-bit value in to an "r0 = add(rX, #a)" instruction by overwriting the source register bits. Since r0 is the return value register, if this instruction is placed after a function call which return void, r0 will be filled with an undefined value, the prefetch won't be confused, and the callee can access the constant value by way of the link register. llvm-svn: 261006
*	[NFC] Fixing naming convention, lowercase start of function name.	Colin LeMahieu	2016-02-15	1	-1/+1
\| \| \| \|	llvm-svn: 260903
*	[Hexagon] Wrapping all MCExprs inside MCOperands within HexagonMCExpr to ↵	Colin LeMahieu	2016-02-15	1	-13/+28
\| \| \| \| \| \|	simplify handling and allow flags on the expression. llvm-svn: 260902
*	[Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction ↵	Colin LeMahieu	2015-11-09	1	-0/+49
	parsing tests. General updating of the code emission. llvm-svn: 252443