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path: root/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h
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* [Hexagon] Fix uninitialized value caught with valgrindKrzysztof Parzyszek2017-05-021-1/+1
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301957
* [Hexagon] Don't ignore mult-cycle latency informationKrzysztof Parzyszek2017-05-021-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | The compiler was generating code that ends up ignoring a multiple latency dependence between two instructions by scheduling the intructions in back-to-back packets. The packetizer needs to end a packet if the latency of the current current insruction and the source in the previous packet is greater than 1 cycle. This case occurs when there is still room in the current packet, but scheduling the instruction causes a stall. Instead, the packetizer should start a new packet. Also, if the current packet already contains a stall, then it is okay to add another instruction to the packet that also causes a stall. This occurs when there are no instructions that can be scheduled in between the producer and consumer instructions. This patch changes the latency for loads to 2 cycles from 3 cycles. This change refects that a load only needs to be separated by one extra packet to eliminate the stall. Patch by Ikhlas Ajbar. llvm-svn: 301954
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-171-0/+1
| | | | | | Reapply r295371 with a fix for the Windows bot failures. llvm-svn: 295504
* Revert "[Hexagon] Start using regmasks on calls"Rafael Espindola2017-02-171-1/+0
| | | | | | | | | | This reverts commit r295371. It broke windows bots: http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio llvm-svn: 295402
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-161-0/+1
| | | | | | All the cool targets are doing it... llvm-svn: 295371
* [Hexagon] Make header self-contained.Benjamin Kramer2017-01-301-0/+3
| | | | llvm-svn: 293482
* [Hexagon] Referencify MachineInstr in HexagonInstrInfo, NFCKrzysztof Parzyszek2016-07-291-23/+23
| | | | llvm-svn: 277220
* [Hexagon] Post-increment loads/stores enhancementsKrzysztof Parzyszek2016-07-261-1/+1
| | | | | | | - Generate vector post-increment stores more aggressively. - Predicate post-increment and vector stores in early if-conversion. llvm-svn: 276800
* [Hexagon] Update store offset when not packetizing it with allocframeKrzysztof Parzyszek2016-07-261-0/+2
| | | | | | | | | | When the packetizer wants to put a store to a stack slot in the same packet with an allocframe, it updates the store offset to reflect the value of SP before it is updated by allocframe. If the store cannot be packetized with the allocframe after all, the offset needs to be updated back to the previous value. llvm-svn: 276749
* CodeGen: Update DFAPacketizer API to take MachineInstr&, NFCDuncan P. N. Exon Smith2016-02-271-5/+6
| | | | | | | | | In all but one case, change the DFAPacketizer API to take MachineInstr& instead of MachineInstr*. In DFAPacketizer::endPacket(), take MachineBasicBlock::iterator. Besides cleaning up the API, this is in search of PR26753. llvm-svn: 262142
* CodeGen: TII: Take MachineInstr& in predicate API, NFCDuncan P. N. Exon Smith2016-02-231-1/+1
| | | | | | | | | | | | | Change TargetInstrInfo API to take `MachineInstr&` instead of `MachineInstr*` in the functions related to predicated instructions (I'll try to come back later and get some of the rest). All of these functions require non-null parameters already, so references are more clear. As a bonus, this happens to factor away a host of implicit iterator => pointer conversions. No functionality change intended. llvm-svn: 261605
* [Hexagon] Update the Hexagon packetizerKrzysztof Parzyszek2015-12-161-0/+114
llvm-svn: 255807
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