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path: root/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
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* [Hexagon] Removing more V4 predicates since V4 is the required minimum.Colin LeMahieu2015-02-091-76/+68
| | | | llvm-svn: 228614
* [Hexagon] Renaming Y2_barrier. Fixing issues where doubleword variants of ↵Colin LeMahieu2015-02-051-1/+1
| | | | | | instructions can't be newvalue producers. llvm-svn: 228330
* [Hexagon] Updating call/jump instruction patterns.Colin LeMahieu2015-01-161-2/+1
| | | | llvm-svn: 226288
* [Hexagon] Updating constant extender def, adding alu-not instructions, ↵Colin LeMahieu2014-12-301-3/+3
| | | | | | compare to general register, and inverted compares. llvm-svn: 224989
* [Hexagon] Adding allocframe, post-increment circular immediate stores, ↵Colin LeMahieu2014-12-291-3/+3
| | | | | | post-increment circular register stores, and bit reversed post-increment stores. llvm-svn: 224957
* [Hexagon] Adding post-increment register form stores and register-immediate ↵Colin LeMahieu2014-12-291-3/+3
| | | | | | form stores with tests. llvm-svn: 224952
* [Hexagon] Adding deallocframe and circular addressing loads.Colin LeMahieu2014-12-261-1/+1
| | | | llvm-svn: 224869
* [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.Colin LeMahieu2014-12-191-2/+2
| | | | llvm-svn: 224556
* Reverting 224550, was not ready for commit.Colin LeMahieu2014-12-181-2/+2
| | | | llvm-svn: 224552
* [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.Colin LeMahieu2014-12-181-2/+2
| | | | llvm-svn: 224550
* [Hexagon] Adding encodings for JR class instructions. Updating complier usages.Colin LeMahieu2014-12-101-2/+2
| | | | llvm-svn: 223967
* Remove the TargetMachine from DFAPacketizer since it was onlyEric Christopher2014-10-141-4/+4
| | | | | | | being used to grab subtarget specific things that we can grab from the MachineFunction anyhow. llvm-svn: 219650
* Remove unnecessary copying or replace it with moves in a bunch of places.Benjamin Kramer2014-10-041-42/+40
| | | | | | NFC. llvm-svn: 219061
* Spelling correctionSid Manning2014-09-081-2/+2
| | | | | | Another trivial spelling change. llvm-svn: 217364
* Cleanup: Delete seemingly unused reference to MachineDominatorTree from ↵Alexey Samsonov2014-08-201-6/+4
| | | | | | ScheduleDAGInstrs. llvm-svn: 216124
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-2/+1
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-9/+10
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-9/+10
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Hexagon edition llvm-svn: 207508
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-2/+2
| | | | llvm-svn: 207197
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-041-1/+1
| | | | llvm-svn: 205610
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-4/+4
| | | | | | Remove the old functions. llvm-svn: 202636
* Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth2014-01-071-20/+19
| | | | | | | | | | subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. llvm-svn: 198685
* Correct word hyphenationsAlp Toker2013-12-051-1/+1
| | | | | | | This patch tries to avoid unrelated changes other than fixing a few hyphen-related ambiguities and contractions in nearby lines. llvm-svn: 196471
* Hexagon: Make helper functions static.Benjamin Kramer2013-05-231-1/+2
| | | | llvm-svn: 182588
* Hexagon: ArePredicatesComplement should not restrict itself to TFRs.Jyotsna Verma2013-05-141-5/+31
| | | | llvm-svn: 181803
* Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore.Jyotsna Verma2013-05-101-707/+20
| | | | | | No functionality change. llvm-svn: 181628
* Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.Jyotsna Verma2013-05-101-534/+18
| | | | llvm-svn: 181624
* Hexagon: Remove switch cases from GetDotNewPredOp and isPostIncrement functions.Jyotsna Verma2013-05-091-516/+1
| | | | | | No functionality change. llvm-svn: 181535
* Print IR from Hexagon MI passes with -print-before/after-all.Krzysztof Parzyszek2013-05-061-3/+1
| | | | llvm-svn: 181255
* Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.Jyotsna Verma2013-05-061-3/+2
| | | | llvm-svn: 181235
* Hexagon: Honor __builtin_expect by using branch probabilities.Jyotsna Verma2013-05-021-22/+57
| | | | | | | | | | | | | * lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp): Given a jump opcode return the right pred.new jump opcode with a taken vs not-taken hint based on branch probabilities provided by the target independent module. * lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function. * lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode): Enhance existing function use branch probabilities like HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps. llvm-svn: 180923
* Hexagon: Use multiclass for Jump instructions.Jyotsna Verma2013-05-011-18/+18
| | | | llvm-svn: 180885
* Hexagon: Replace switch-case in isDotNewInst with TSFlags.Jyotsna Verma2013-03-281-172/+5
| | | | llvm-svn: 178281
* Hexagon: Use MO operand flags to mark constant extended instructions.Jyotsna Verma2013-03-051-15/+5
| | | | llvm-svn: 176500
* Hexagon: Add constant extender support framework.Jyotsna Verma2013-03-011-23/+24
| | | | llvm-svn: 176358
* Hexagon: Use absolute addressing mode loads/stores for global+offset Jyotsna Verma2013-02-131-278/+1
| | | | | | instead of redefining separate instructions for them. llvm-svn: 175086
* Replace LDriu*[bhdw]_indexed_V4 instructions with "def Pats".Jyotsna Verma2013-02-011-108/+0
| | | | llvm-svn: 174193
* Add TSFlags to ALU32 type instructions for constant-extender/Relationship maps.Jyotsna Verma2012-12-201-5/+7
| | | | llvm-svn: 170671
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-20/+19
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Rename hasVolatileMemoryRef() to hasOrderedMemoryRef().Jakob Stoklund Olesen2012-08-291-2/+2
| | | | | | | | Ordered memory operations are more constrained than volatile loads and stores because they must be ordered with respect to all other memory operations. llvm-svn: 162861
* Revert r158679 - use case is unclear (and it increases the memory footprint).Hal Finkel2012-06-221-1/+1
| | | | | | | | | | Original commit message: Allow up to 64 functional units per processor itinerary. This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. llvm-svn: 159027
* Allow up to 64 functional units per processor itinerary.Hal Finkel2012-06-181-1/+1
| | | | | | | This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. llvm-svn: 158679
* Revert 156634 upon request until code improvement changes are made.Brendon Cahoon2012-05-141-455/+4
| | | | llvm-svn: 156775
* Remove warnings from HexagonVLIWPacketizer.Sirish Pande2012-05-111-3/+3
| | | | llvm-svn: 156636
* Hexagon constant extender support.Brendon Cahoon2012-05-111-4/+455
| | | | | | Patch by Jyotsna Verma. llvm-svn: 156634
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-1/+1
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* Support for target dependent Hexagon VLIW packetizer.Sirish Pande2012-05-031-0/+3646
| | | | | | This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
* Revert r155365, r155366, and r155367. All three of these have regressionChandler Carruth2012-04-231-3640/+0
| | | | | | | | | | | test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. llvm-svn: 155372
* Support for Hexagon VLIW Packetizer.Sirish Pande2012-04-231-0/+3640
| | | | llvm-svn: 155365
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