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* [ARM] Teach the Arm cost model that a Shift can be folded into other ↵David Green2019-12-091-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | instructions This attempts to teach the cost model in Arm that code such as: %s = shl i32 %a, 3 %a = and i32 %s, %b Can under Arm or Thumb2 become: and r0, r1, r2, lsl #3 So the cost of the shift can essentially be free. To do this without trying to artificially adjust the cost of the "and" instruction, it needs to get the users of the shl and check if they are a type of instruction that the shift can be folded into. And so it needs to have access to the actual instruction in getArithmeticInstrCost, which if available is added as an extra parameter much like getCastInstrCost. We otherwise limit it to shifts with a single user, which should hopefully handle most of the cases. The list of instruction that the shift can be folded into include ADC, ADD, AND, BIC, CMP, EOR, MVN, ORR, ORN, RSB, SBC and SUB. This translates to Add, Sub, And, Or, Xor and ICmp. Differential Revision: https://reviews.llvm.org/D70966
* [Alignment][NFC] getMemoryOpCost uses MaybeAlignGuillaume Chatelet2019-10-251-11/+20
| | | | | | | | | | | | | | | Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: nemanjai, hiraditya, kbarton, MaskRay, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69307
* [SVE][MVT] Fixed-length vector MVT rangesGraham Hunter2019-09-171-0/+2
| | | | | | | | | | | | | | | | | * Reordered MVT simple types to group scalable vector types together. * New range functions in MachineValueType.h to only iterate over the fixed-length int/fp vector types. * Stopped backends which don't support scalable vector types from iterating over scalable types. Reviewers: sdesmalen, greened Reviewed By: greened Differential Revision: https://reviews.llvm.org/D66339 llvm-svn: 372099
* [Hexagon] assert getRegisterBitWidth returns non-zero value. NFCI.Simon Pilgrim2019-05-221-2/+3
| | | | | | Fixes scan-build warning. llvm-svn: 361375
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [TargetLowering] Change TargetLoweringBase::getPreferredVectorAction to take ↵Craig Topper2018-11-051-1/+1
| | | | | | | | an MVT instead of an EVT. NFC The main caller of this already has an MVT and several targets called getSimpleVT inside without checking isSimple. This makes the simpleness explicit. llvm-svn: 346180
* [LV] Support vectorization of interleave-groups that require an epilog underDorit Nuzman2018-10-311-3/+5
| | | | | | | | | | | | | | | | | | | | | | optsize using masked wide loads Under Opt for Size, the vectorizer does not vectorize interleave-groups that have gaps at the end of the group (such as a loop that reads only the even elements: a[2*i]) because that implies that we'll require a scalar epilogue (which is not allowed under Opt for Size). This patch extends the support for masked-interleave-groups (introduced by D53011 for conditional accesses) to also cover the case of gaps in a group of loads; Targets that enable the masked-interleave-group feature don't have to invalidate interleave-groups of loads with gaps; they could now use masked wide-loads and shuffles (if that's what the cost model selects). Reviewers: Ayal, hsaito, dcaballe, fhahn Reviewed By: Ayal Differential Revision: https://reviews.llvm.org/D53668 llvm-svn: 345705
* Revert r345169 [along with its llvm counterpart r345170] as it makes Halide ↵Alina Sbirlea2018-10-271-1/+1
| | | | | | builds timeout. llvm-svn: 345447
* [Hexagon] Flip hexagon-autohvx to be true by defaultKrzysztof Parzyszek2018-10-241-1/+1
| | | | | | | | | | | This will allow other generators of LLVM IR to use the auto-vectorizer without having to change that flag. Note: on its own, this patch will enable auto-vectorization on Hexagon in all cases, regardless of the -fvectorize flag. There is a companion clang patch that together with this one forms an NFC for clang users. llvm-svn: 345169
* recommit 344472 after fixing build failure on ARM and PPC.Dorit Nuzman2018-10-141-3/+3
| | | | llvm-svn: 344475
* revert 344472 due to failures.Dorit Nuzman2018-10-141-3/+3
| | | | llvm-svn: 344473
* [IAI,LV] Add support for vectorizing predicated strided accesses using maskedDorit Nuzman2018-10-141-3/+3
| | | | | | | | | | | | | | | | | | | | | | | interleave-group The vectorizer currently does not attempt to create interleave-groups that contain predicated loads/stores; predicated strided accesses can currently be vectorized only using masked gather/scatter or scalarization. This patch makes predicated loads/stores candidates for forming interleave-groups during the Loop-Vectorizer's analysis, and adds the proper support for masked-interleave- groups to the Loop-Vectorizer's planning and transformation stages. The patch also extends the TTI API to allow querying the cost of masked interleave groups (which each target can control); Targets that support masked vector loads/ stores may choose to enable this feature and allow vectorizing predicated strided loads/stores using masked wide loads/stores and shuffles. Reviewers: Ayal, hsaito, dcaballe, fhahn, javed.absar Reviewed By: Ayal Differential Revision: https://reviews.llvm.org/D53011 llvm-svn: 344472
* [Hexagon] Enable interleaving in loop vectorizerKrzysztof Parzyszek2018-08-221-2/+4
| | | | llvm-svn: 340447
* [Hexagon] Make floating point operations expensive for vectorizationKrzysztof Parzyszek2018-06-121-6/+30
| | | | llvm-svn: 334508
* [Hexagon] hexagon-autohvx was left on againKrzysztof Parzyszek2018-04-201-1/+1
| | | | llvm-svn: 330472
* [Hexagon] Improve HVX instruction selection (bitcast, vsplat)Krzysztof Parzyszek2018-04-201-1/+1
| | | | | | | | | | There was some unfortunate interaction between VSPLAT and BITCAST related to the selection of constant vectors (coming from selecting shuffles). Introduce VSPLATW that always splats a 32-bit word, and can have arbitrary result type (to avoid BITCASTs of VSPLAT). Clean up the previous selection of BITCAST/VSPLAT. llvm-svn: 330471
* [Hexagon] Turn off flag enabling auto-vectorizationKrzysztof Parzyszek2018-04-161-1/+1
| | | | | | It was turned on for testing and was accidentally left on in the commit. llvm-svn: 330139
* [Hexagon] Initial instruction cost model for auto-vectorizationKrzysztof Parzyszek2018-04-131-15/+160
| | | | llvm-svn: 330065
* [LV] Introduce TTI::getMinimumVFKrzysztof Parzyszek2018-04-131-0/+4
| | | | | | | | | | | The function getMinimumVF(ElemWidth) will return the minimum VF for a vector with elements of size ElemWidth bits. This value will only apply to targets for which TTI::shouldMaximizeVectorBandwidth returns true. The value of 0 indicates that there is no minimum VF. Differential Revision: https://reviews.llvm.org/D45271 llvm-svn: 330062
* [Hexagon] peel loops with runtime small trip countsIkhlas Ajbar2018-04-031-1/+2
| | | | | | | | Move the check canPeel() to Hexagon Target before setting PeelCount. Differential Revision: https://reviews.llvm.org/D44880 llvm-svn: 329129
* peel loops with runtime small trip countsIkhlas Ajbar2018-04-031-0/+7
| | | | | | | | | | For Hexagon, peeling loops with small runtime trip count is beneficial for our benchmarks. We set PeelCount in HexagonTargetInfo.cpp and we use PeelCount set by the target for computing the desired peel count. Differential Revision: https://reviews.llvm.org/D44880 llvm-svn: 329042
* Revert "peel loops with runtime small trip counts"Krzysztof Parzyszek2018-03-301-8/+0
| | | | | | This reverts commit r328854, it breaks some Hexagon tests. llvm-svn: 328875
* peel loops with runtime small trip countsIkhlas Ajbar2018-03-301-0/+8
| | | | | | | | | | For Hexagon, peeling loops with small runtime trip count is beneficial for our benchmarks. We set PeelCount in HexagonTargetInfo.cpp and we use PeelCount set by the target for computing the desired peel count. Differential Revision: https://reviews.llvm.org/D44880 llvm-svn: 328854
* [Hexagon] Rudimentary support for auto-vectorization for HVXKrzysztof Parzyszek2018-03-271-11/+48
| | | | | | | | This implements a set of TTI functions that the loop vectorizer uses. The only purpose of this is to enable testing. Auto-vectorization is disabled by default, enabled by -hexagon-autohvx. llvm-svn: 328639
* [Hexagon] Give priority to post-incremementing memory accesses in LSRKrzysztof Parzyszek2018-03-261-1/+5
| | | | llvm-svn: 328506
* [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-08-011-2/+7
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 309746
* [Hexagon] Guard the generation of lookup tableSumanth Gundapaneni2017-06-301-0/+8
| | | | | | | | The llvm flag "-hexagon-emit-lookup-tables" guards the generation of lookup table generated from a switch statement. Differential Revision: https://reviews.llvm.org/D34819 llvm-svn: 306877
* [TargetTransformInfo, API] Add a list of operands to TTI::getUserCostEvgeny Astigeevich2017-06-291-3/+4
| | | | | | | | | | | | | | | | | | | | The changes are a result of discussion of https://reviews.llvm.org/D33685. It solves the following problem: 1. We can inform getGEPCost about simplified indices to help it with calculating the cost. But getGEPCost does not take into account the context which GEPs are used in. 2. We have getUserCost which can take the context into account but we cannot inform about simplified indices. With the changes getUserCost will have access to additional information as getGEPCost has. The one parameter getUserCost is also provided. Differential Revision: https://reviews.llvm.org/D34057 llvm-svn: 306674
* [LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI.Geoff Berry2017-06-281-1/+1
| | | | | | | | | | Reviewers: sanjoy, anna, reames, apilipenko, igor-laevsky, mkuper Subscribers: jholewinski, arsenm, mzolotukhin, nemanjai, nhaehnle, javed.absar, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D34531 llvm-svn: 306554
* [Hexagon] Consider zext/sext of a load to i32 to be freeKrzysztof Parzyszek2016-08-191-0/+25
| | | | llvm-svn: 279248
* [Hexagon] Use loop data prefetch on HexagonKrzysztof Parzyszek2016-07-221-0/+8
| | | | llvm-svn: 276422
* [Hexagon] Edit a comment. NFCKrzysztof Parzyszek2015-08-051-7/+1
| | | | llvm-svn: 244130
* [Hexagon] Implement TargetTransformInfo for HexagonKrzysztof Parzyszek2015-08-051-0/+44
Author: Brendon Cahoon <bcahoon@codeaurora.org> llvm-svn: 244089
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