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path: root/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
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* Make MachineScheduler debug output less confusing.James Y Knight2015-09-181-1/+5
| | | | | | At least...a little bit. llvm-svn: 248020
* Move HexagonMachineScheduler to use the subtarget off of theEric Christopher2015-02-021-9/+6
| | | | | | | MachineFunction and update all uses accordingly including VLIWResourceModel. llvm-svn: 227872
* Fix null reference creation in ScheduleDAGInstrs constructor call.Alexey Samsonov2014-08-201-1/+1
| | | | | | | | | Both MachineLoopInfo and MachineDominatorTree may be null in ScheduleDAGMI constructor call. It is undefined behavior to take references to these values. This bug is reported by UBSan. llvm-svn: 216118
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-2/+6
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Fix 'platform-specific' hyphenationsAlp Toker2014-06-301-2/+2
| | | | llvm-svn: 212056
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-8/+8
| | | | llvm-svn: 207197
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-2/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* Replace PROLOG_LABEL with a new CFI_INSTRUCTION.Rafael Espindola2014-03-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | The old system was fairly convoluted: * A temporary label was created. * A single PROLOG_LABEL was created with it. * A few MCCFIInstructions were created with the same label. The semantics were that the cfi instructions were mapped to the PROLOG_LABEL via the temporary label. The output position was that of the PROLOG_LABEL. The temporary label itself was used only for doing the mapping. The new CFI_INSTRUCTION has a 1:1 mapping to MCCFIInstructions and points to one by holding an index into the CFI instructions of this function. I did consider removing MMI.getFrameInstructions completelly and having CFI_INSTRUCTION own a MCCFIInstruction, but MCCFIInstructions have non trivial constructors and destructors and are somewhat big, so the this setup is probably better. The net result is that we don't create temporary labels that are never used. llvm-svn: 203204
* Factor MI-Sched in preparation for post-ra scheduling support.Andrew Trick2013-12-281-7/+10
| | | | | | | | Factor the MachineFunctionPass into MachineSchedulerBase. Split the DAG class into ScheduleDAGMI and SchedulerDAGMILive. llvm-svn: 198119
* Rename variables for consistency.Eli Friedman2013-09-111-3/+3
| | | | | | No functional change. llvm-svn: 190466
* Fix unused variables.Eli Friedman2013-09-101-2/+0
| | | | llvm-svn: 190448
* mi-sched: Precompute a PressureDiff for each instruction, adjust for ↵Andrew Trick2013-08-301-5/+5
| | | | | | | | | | | | | liveness later. Created SUPressureDiffs array to hold the per node PDiff computed during DAG building. Added a getUpwardPressureDelta API that will soon replace the old one. Compute PressureDelta here from the precomputed PressureDiffs. Updating for liveness will come next. llvm-svn: 189640
* Fix a memory leak in the hexagon scheduler. We call initialize here moreChandler Carruth2013-07-271-0/+2
| | | | | | | | | | | | | than once, and the second time through we leaked memory. Found thanks to the vg-leak bot, but I can't locally reproduce it with valgrind. The debugger confirms that it is in fact leaking here. This whole code is totally gross. Why is initialize being called on each runOnFunction??? Why aren't these OwningPtr<>s, and why aren't their lifetimes better defined? Anyways, this is just a surgical change to help out the leak checking bots. llvm-svn: 187299
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-151-2/+2
| | | | | | | | | | | | | Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. llvm-svn: 184032
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-2/+1
| | | | | | the internals of TargetMachine could change. llvm-svn: 183490
* Cleanup #includes.Jakub Staszak2013-03-101-1/+2
| | | | llvm-svn: 176787
* Added FIXME for future Hexagon cleanup.Andrew Trick2013-03-021-0/+3
| | | | llvm-svn: 176400
* MIsched: HazardRecognizers are created for each DAG. Free them.Andrew Trick2013-02-131-1/+3
| | | | llvm-svn: 175067
* MIsched: Improve the interface to SchedDFS analysis (subtrees).Andrew Trick2013-01-251-1/+7
| | | | | | | Allow the strategy to select SchedDFS. Allow the results of SchedDFS to affect initialization of the scheduler state. llvm-svn: 173425
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-1/+0
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.Andrew Trick2012-11-061-2/+1
| | | | | | | This is in preparation for adding "weak" DAG edges, but generally simplifies the design. llvm-svn: 167435
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-101-10/+13
| | | | | | | | Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. llvm-svn: 165603
* DAG post-process for Hexagon MI schedulerSergei Larin2012-09-141-0/+27
| | | | | | | | This patch introduces a possibility for Hexagon MI scheduler to perform some target specific post- processing on the scheduling DAG prior to scheduling. llvm-svn: 163903
* Remove redundant private field.Benjamin Kramer2012-09-141-1/+1
| | | | | | clang warned about this being unused in Release builds. llvm-svn: 163899
* Reorganize MachineScheduler interfaces and publish them in the header.Andrew Trick2012-09-111-312/+12
| | | | | | | | | | | | | | The Hexagon target decided to use a lot of functionality from the target-independent scheduler. That's fine, and other targets should be able to do the same. This reorg and API update makes that easy. For the record, ScheduleDAGMI was not meant to be subclassed. Instead, new scheduling algorithms should be able to implement MachineSchedStrategy and be done. But if need be, it's nice to be able to extend ScheduleDAGMI, so I also made that easier. The target scheduler is somewhat more apt to break that way though. llvm-svn: 163580
* Add "blocked" heuristic to the Hexagon MI scheduler.Sergei Larin2012-09-101-36/+114
| | | | | | Improve AQ instruction selection in the Hexagon MI scheduler. llvm-svn: 163523
* Porting Hexagon MI Scheduler to the new API.Sergei Larin2012-09-041-0/+874
Change current Hexagon MI scheduler to use new converging scheduler. Integrates DFA resource model into it. llvm-svn: 163137
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