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* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-71/+73
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [HexagonMachineScheduler] Remove local (copied) getWeakLeft().Jonas Paulsson2018-04-121-4/+0
| | | | | | | Since the common code getWeakLeft() is now available, there should not be a local copy of this function in target. llvm-svn: 329885
* [Hexagon] Add heuristic to exclude critical path cost for schedulingKrzysztof Parzyszek2018-03-201-173/+75
| | | | | | Patch by Brendon Cahoon. llvm-svn: 328022
* [Hexagon] Correct the computation of TopReadyCycle and BotReadyCycle of SUKrzysztof Parzyszek2018-03-201-13/+5
| | | | | | | | | TopReadyCycle and BotReadyCycle were off by one cycle when an SU is either the first instruction or the last instruction in a packet. Patch by Ikhlas Ajbar. llvm-svn: 328000
* [Hexagon] Check weak dependences when only 1 instruction is availableKrzysztof Parzyszek2018-03-201-9/+13
| | | | | | Patch by Brendon Cahoon. llvm-svn: 327997
* [Hexagon] Improve scheduling heuristic for large basic blocksKrzysztof Parzyszek2018-03-201-3/+11
| | | | | | | | | | | | | | | | | | | | This patch changes the isLatencyBound heuristic to look at the path length based upon the number of packets needed to schedule a basic block. For small basic blocks, the heuristic uses a small threshold for isLatencyBound. For large basic blocks, the heuristic uses a large threshold. The goal is to increase the priority of an instruction in a small basic block that has a large height or depth relative to the code size. For large functions, the height and depth are ignored because it increases the live range of a register and causes more spills. That is, for large functions, it is more important to schedule instructions when available, and attempt to keep the defs and uses closer together. Patch by Brendon Cahoon. llvm-svn: 327987
* [Hexagon] Fix division by zero in machine schedulerKrzysztof Parzyszek2018-03-201-1/+1
| | | | llvm-svn: 327980
* [Hexagon] Improve scheduling based on register pressureKrzysztof Parzyszek2018-03-201-60/+203
| | | | | | Patch by Brendon Cahoon. llvm-svn: 327975
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-1/+1
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-8/+6
| | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-3/+3
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
| | | | | | | | This header includes CodeGen headers, and is not, itself, included by any Target headers, so move it into CodeGen to match the layering of its implementation. llvm-svn: 317647
* [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-09-281-10/+31
| | | | | | other minor fixes (NFC). llvm-svn: 314467
* [Hexagon] Break up DAG mutations into separate classes, move to subtargetKrzysztof Parzyszek2017-08-281-79/+0
| | | | llvm-svn: 311895
* [Hexagon] Move pre-RA DAG mutations to scheduler constructorKrzysztof Parzyszek2017-08-281-13/+1
| | | | llvm-svn: 311894
* [CodeGen] Rename DEBUG_TYPE to match passnamesEvandro Menezes2017-07-111-1/+1
| | | | | | | | | Rename missing DEBUG_TYPE "machine-scheduler" from backend files, which were absent from https://reviews.llvm.org/rL303921. Differential revision: https://reviews.llvm.org/D35231 llvm-svn: 307719
* [Hexagon] Speedup NumNodesBlocking calculation. NFCI.Nirav Dave2017-06-081-32/+25
| | | | llvm-svn: 305003
* [Hexagon] Use automatically-generated scheduling information for HVXKrzysztof Parzyszek2017-05-031-1/+1
| | | | | | Patch by Jyotsna Verma. llvm-svn: 302073
* [Hexagon] Update instruction typesKrzysztof Parzyszek2017-02-071-1/+3
| | | | | | | | | Remove TypeXTYPE, TypeALU32, TypeSYSTEM, TypeJR, and instead use their architecture counterparts. Patch by Colin LeMahieu. llvm-svn: 294321
* Move helpers into anonymous namespaces. NFC.Benjamin Kramer2016-08-061-0/+2
| | | | llvm-svn: 277916
* [Hexagon] Referencify MachineInstr in HexagonInstrInfo, NFCKrzysztof Parzyszek2016-07-291-8/+8
| | | | llvm-svn: 277220
* [Hexagon] Misc changes to HexagonMachineScheduler, NFCKrzysztof Parzyszek2016-07-181-26/+3
| | | | | | | - Remove duplicated code. - Convert loop to range-for. llvm-svn: 275806
* [Hexagon] Enable .cur formation in MISched for Hexagon V60Krzysztof Parzyszek2016-07-181-0/+8
| | | | | | | | | | | Schedule a load and its use in the same packet in MISched. Previously, isResourceAvailable was returning false for dependences in the same packet, which prevented MISched from packetizing a load and its use in the same packet for v60. Patch by Ikhlas Ajbar. llvm-svn: 275804
* [Hexagon] Add verbose debugging mode to Hexagon MI SchedulerKrzysztof Parzyszek2016-07-181-8/+71
| | | | | | Patch by Sergei Larin. llvm-svn: 275799
* [Hexagon] Use timing class info as tie-breaker in machine schedulerKrzysztof Parzyszek2016-07-181-0/+66
| | | | | | Patch by Sirish Pande. llvm-svn: 275794
* [Hexagon] HexagonMachineScheduler should account for resourcesKrzysztof Parzyszek2016-07-181-10/+78
| | | | | | | | | | | | | | | | | The machine scheduler needs to account for available resources more accurately in order to avoid scheduling an instruction that forces a new packet to be created. This occurs in two ways: First, an instruction without an available resource may have a large priority due to other metrics and be scheduled when there are other instructions with available resources. Second, an instruction with a non-zero latency may become available prematurely. In both these cases, we attempt change the priority in order to allow a better instruction to be scheduled. Patch by Brendon Cahoon. llvm-svn: 275793
* [Hexagon] Fix zero latency instructions with multiple predecessorsKrzysztof Parzyszek2016-07-181-2/+30
| | | | | | | | | | | An instruction may have multiple predecessors that are candidates for using .cur. However, only one of them can use .cur in the packet. When this case occurs, we need to make sure that only one of the dependences gets a 0 latency value. Patch by Brendon Cahoon. llvm-svn: 275790
* [Hexagon] Handle instruction latency for 0 or 2 cyclesKrzysztof Parzyszek2016-07-151-0/+22
| | | | | | | | | | | | | | | | | | | | | | | The Hexagon schedulers need to handle instructions with a latency of 0 or 2 more accurately. The problem, in v60, is that a dependence between two instructions with a 2 cycle latency can use a .cur version of the source to achieve a 0 cycle latency when the use is in the same packet. Any othe use, must be at least 2 packets later, or a stall occurs. In other words, the compiler does not want to schedule the dependent instructions 1 cycle later. To achieve this, the latency adjustment code allows only a single dependence to have a zero latency. All other instructions have the other value, which is typically 2 cycles. We use a heuristic to determine which instruction gets the 0 latency. The Hexagon machine scheduler was also changed to increase the cost associated with 0 latency dependences than can be scheduled in the same packet. Patch by Brendon Cahoon. llvm-svn: 275625
* [Hexagon] Make MI scheduler check for stalls in previous packet on v60Krzysztof Parzyszek2016-07-151-0/+28
| | | | | | Patch by Ikhlas Ajbar. llvm-svn: 275606
* [Hexagon] Replace postprocessDAG with a more elaborate DAG mutationKrzysztof Parzyszek2016-07-151-10/+76
| | | | llvm-svn: 275598
* [Hexagon] Add a scheduling DAG mutationKrzysztof Parzyszek2016-07-151-0/+4
| | | | | | | - Remove output dependencies on USR_OVF register. - Update chain edge latencies between v60 vector loads/stores. llvm-svn: 275586
* CodeGen: Update DFAPacketizer API to take MachineInstr&, NFCDuncan P. N. Exon Smith2016-02-271-2/+2
| | | | | | | | | In all but one case, change the DFAPacketizer API to take MachineInstr& instead of MachineInstr*. In DFAPacketizer::endPacket(), take MachineBasicBlock::iterator. Besides cleaning up the API, this is in search of PR26753. llvm-svn: 262142
* Make MachineScheduler debug output less confusing.James Y Knight2015-09-181-1/+5
| | | | | | At least...a little bit. llvm-svn: 248020
* Move HexagonMachineScheduler to use the subtarget off of theEric Christopher2015-02-021-9/+6
| | | | | | | MachineFunction and update all uses accordingly including VLIWResourceModel. llvm-svn: 227872
* Fix null reference creation in ScheduleDAGInstrs constructor call.Alexey Samsonov2014-08-201-1/+1
| | | | | | | | | Both MachineLoopInfo and MachineDominatorTree may be null in ScheduleDAGMI constructor call. It is undefined behavior to take references to these values. This bug is reported by UBSan. llvm-svn: 216118
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-2/+6
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Fix 'platform-specific' hyphenationsAlp Toker2014-06-301-2/+2
| | | | llvm-svn: 212056
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-8/+8
| | | | llvm-svn: 207197
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-2/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* Replace PROLOG_LABEL with a new CFI_INSTRUCTION.Rafael Espindola2014-03-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | The old system was fairly convoluted: * A temporary label was created. * A single PROLOG_LABEL was created with it. * A few MCCFIInstructions were created with the same label. The semantics were that the cfi instructions were mapped to the PROLOG_LABEL via the temporary label. The output position was that of the PROLOG_LABEL. The temporary label itself was used only for doing the mapping. The new CFI_INSTRUCTION has a 1:1 mapping to MCCFIInstructions and points to one by holding an index into the CFI instructions of this function. I did consider removing MMI.getFrameInstructions completelly and having CFI_INSTRUCTION own a MCCFIInstruction, but MCCFIInstructions have non trivial constructors and destructors and are somewhat big, so the this setup is probably better. The net result is that we don't create temporary labels that are never used. llvm-svn: 203204
* Factor MI-Sched in preparation for post-ra scheduling support.Andrew Trick2013-12-281-7/+10
| | | | | | | | Factor the MachineFunctionPass into MachineSchedulerBase. Split the DAG class into ScheduleDAGMI and SchedulerDAGMILive. llvm-svn: 198119
* Rename variables for consistency.Eli Friedman2013-09-111-3/+3
| | | | | | No functional change. llvm-svn: 190466
* Fix unused variables.Eli Friedman2013-09-101-2/+0
| | | | llvm-svn: 190448
* mi-sched: Precompute a PressureDiff for each instruction, adjust for ↵Andrew Trick2013-08-301-5/+5
| | | | | | | | | | | | | liveness later. Created SUPressureDiffs array to hold the per node PDiff computed during DAG building. Added a getUpwardPressureDelta API that will soon replace the old one. Compute PressureDelta here from the precomputed PressureDiffs. Updating for liveness will come next. llvm-svn: 189640
* Fix a memory leak in the hexagon scheduler. We call initialize here moreChandler Carruth2013-07-271-0/+2
| | | | | | | | | | | | | than once, and the second time through we leaked memory. Found thanks to the vg-leak bot, but I can't locally reproduce it with valgrind. The debugger confirms that it is in fact leaking here. This whole code is totally gross. Why is initialize being called on each runOnFunction??? Why aren't these OwningPtr<>s, and why aren't their lifetimes better defined? Anyways, this is just a surgical change to help out the leak checking bots. llvm-svn: 187299
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-151-2/+2
| | | | | | | | | | | | | Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. llvm-svn: 184032
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-2/+1
| | | | | | the internals of TargetMachine could change. llvm-svn: 183490
* Cleanup #includes.Jakub Staszak2013-03-101-1/+2
| | | | llvm-svn: 176787
* Added FIXME for future Hexagon cleanup.Andrew Trick2013-03-021-0/+3
| | | | llvm-svn: 176400
* MIsched: HazardRecognizers are created for each DAG. Free them.Andrew Trick2013-02-131-1/+3
| | | | llvm-svn: 175067
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