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path: root/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
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* [Hexagon] Mark vector loads as predicable, update instruction mappingsKrzysztof Parzyszek2017-10-181-0/+25
| | | | | | | | All loads of form V6_vL32b_{,cur,nt,tmp,nt_cur,nt_tmp}_{ai,pi,ppu} are predicable on v62 (but not on v60). Mark them all as predicable in the instruction definitions, and handle the v60 case in HII::isPredicable. llvm-svn: 316098
* [Hexagon] Handle non-immediate operands to A2_addi in getIncrementValueKrzysztof Parzyszek2017-10-111-4/+6
| | | | llvm-svn: 315472
* [Pipeliner] Fix offset value for instrs dependent on post-inc load/storesKrzysztof Parzyszek2017-10-111-7/+8
| | | | | | | | | | | | The software pipeliner and the packetizer try to break dependence between the post-increment instruction and the dependent memory instructions by changing the base register and the offset value. However, in some cases, the existing logic didn't work properly and created incorrect offset value. Patch by Jyotsna Verma. llvm-svn: 315468
* [Pipeliner] Improve serialization order for post-incrementsKrzysztof Parzyszek2017-10-111-1/+6
| | | | | | | | | | | | | | | | | | | The pipeliner is generating a serial sequence that causes poor register allocation when a post-increment instruction appears prior to the use of the post-increment register. This occurs when there is a circular set of dependences involved with a sequence of instructions in the same cycle. In this case, there is no serialization of the parallel semantics that will not cause an additional register to be allocated. This patch fixes the problem by changing the instructions so that the post-increment instruction is used by the subsequent instruction, which enables the register allocator to make a better decision and not require another register. Patch by Brendon Cahoon. llvm-svn: 315466
* [Hexagon] Give uniform names to functions changing addressing modes, NFCKrzysztof Parzyszek2017-10-051-26/+29
| | | | | | | | | | | | | | | The new format is changeAddrMode_xx_yy, where xx is the current mode, and yy is the new one. Old name: New name: getBaseWithImmOffset changeAddrMode_abs_io getAbsoluteForm changeAddrMode_io_abs getBaseWithRegOffset changeAddrMode_io_rr xformRegToImmOffset changeAddrMode_rr_io getBaseWithLongOffset changeAddrMode_rr_ur getRegShlForm changeAddrMode_ur_rr llvm-svn: 315013
* [Hexagon] Add a member Subtarget to HexagonInstrInfo, NFCKrzysztof Parzyszek2017-10-041-51/+24
| | | | llvm-svn: 314920
* [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-09-281-85/+90
| | | | | | other minor fixes (NFC). llvm-svn: 314467
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-151-248/+125
| | | | | | | This removes the duplicate HVX instruction set for the 128-byte mode. Single instruction set now works for both modes (64- and 128-byte). llvm-svn: 313362
* [Hexagon] Make getMemAccessSize return size in bytesKrzysztof Parzyszek2017-09-141-13/+18
| | | | | | | | It used to return the actual field value from the instruction descriptor. There is no reason for that, that value is not interesting in any way and the specifics of its encoding in the descriptor should not be exposed. llvm-svn: 313257
* [Hexagon] Fix a bug in r308502: post-inc offset is always 0Krzysztof Parzyszek2017-07-191-2/+2
| | | | llvm-svn: 308510
* [Hexagon] Handle subregisters in areMemAccessesTriviallyDisjointKrzysztof Parzyszek2017-07-191-15/+32
| | | | llvm-svn: 308502
* [Hexagon] Handle subregisters and non-immediates in getBaseAndOffsetKrzysztof Parzyszek2017-07-191-6/+14
| | | | llvm-svn: 308485
* [Hexagon] Add support for nontemporal loads and stores on HVXKrzysztof Parzyszek2017-07-111-1/+29
| | | | | | | | Patch by Michael Wu. Differential Revision: https://reviews.llvm.org/D35104 llvm-svn: 307671
* [Hexagon] Fix check for HMOTF_ConstExtend operand flagKrzysztof Parzyszek2017-07-101-8/+3
| | | | | | This fixes https://llvm.org/PR33718. llvm-svn: 307566
* [Hexagon] Handle Hexagon-specific machine operand target flags in MIRKrzysztof Parzyszek2017-07-101-0/+33
| | | | llvm-svn: 307564
* [Hexagon] Use proper predicate register state when expanding PS_vselectKrzysztof Parzyszek2017-06-271-3/+15
| | | | llvm-svn: 306458
* [Hexagon] Handle cases when the aligned stack pointer is missingKrzysztof Parzyszek2017-06-261-8/+2
| | | | llvm-svn: 306288
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
* [Hexagon] Return 0 from getDotNewPredOp when .new opcode does not existKrzysztof Parzyszek2017-06-021-3/+1
| | | | | | | This allows using this function to test if an instruction can be converted to a .new form. llvm-svn: 304549
* [Hexagon] Fix dependence check in the packetizerKrzysztof Parzyszek2017-06-011-158/+12
| | | | | | | An incorrect check in the packetizer lead to an attempt to convert an unconditional branch to a .new (conditional) form. llvm-svn: 304442
* LivePhysRegs: Rework constructor + documentation; NFCMatthias Braun2017-05-261-2/+2
| | | | | | | - Take reference instead of pointer to a TRI that cannot be nullptr. - Improve documentation comments. llvm-svn: 304038
* [Hexagon] Disable predicated calls by defaultKrzysztof Parzyszek2017-05-051-1/+9
| | | | llvm-svn: 302307
* [Hexagon] Use automatically-generated scheduling information for HVXKrzysztof Parzyszek2017-05-031-82/+60
| | | | | | Patch by Jyotsna Verma. llvm-svn: 302073
* [Hexagon] Handle S2_storerf_io in HexagonInstrInfoKrzysztof Parzyszek2017-05-031-0/+1
| | | | llvm-svn: 302036
* [Hexagon] Misc fixes in HexagonInstrInfo, NFCKrzysztof Parzyszek2017-05-031-15/+2
| | | | | | Formatting changes + remove unused function. llvm-svn: 302035
* [Hexagon] Adjust latency between allocframe and the first store on stackKrzysztof Parzyszek2017-05-031-0/+5
| | | | | | | | | | | | Allocframe and the following stores on the stack have a latency of 2 cycles when not in the same packet. This happens because R29 is needed early by the store instruction. Since one of such stores can be packetized along with allocframe and use old value of R29, we can assign it 0 cycle latency while leaving latency of other stores to the default value of 2 cycles. Patch by Jyotsna Verma. llvm-svn: 302034
* [Hexagon] Handle J2_jumptpt and J2_jumpfpt in HexagonInstrInfoKrzysztof Parzyszek2017-05-031-8/+25
| | | | llvm-svn: 302033
* [Hexagon] Implement undoing .cur instructions in packetizerKrzysztof Parzyszek2017-05-031-0/+22
| | | | | | | | | | | | | The packetizer needs to convert .cur instruction to its regular form if the use is not in the same packet as the .cur. The code in the packetizer handles one type of .cur, which is the vector load case. This patch updates the packetizer so that it can undo all the .cur instructions. In the test case, the .cur is the 128B version, but there are also the post-increment versions. Patch by Brendon Cahoon. llvm-svn: 302032
* [Hexagon] Add memory operands to a rewritten loadKrzysztof Parzyszek2017-05-031-2/+3
| | | | llvm-svn: 302030
* [Hexagon] Reset spill alignment when variable-sized objects are presentKrzysztof Parzyszek2017-05-031-0/+30
| | | | llvm-svn: 302029
* [Hexagon] Don't ignore mult-cycle latency informationKrzysztof Parzyszek2017-05-021-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | The compiler was generating code that ends up ignoring a multiple latency dependence between two instructions by scheduling the intructions in back-to-back packets. The packetizer needs to end a packet if the latency of the current current insruction and the source in the previous packet is greater than 1 cycle. This case occurs when there is still room in the current packet, but scheduling the instruction causes a stall. Instead, the packetizer should start a new packet. Also, if the current packet already contains a stall, then it is okay to add another instruction to the packet that also causes a stall. This occurs when there are no instructions that can be scheduled in between the producer and consumer instructions. This patch changes the latency for loads to 2 cycles from 3 cycles. This change refects that a load only needs to be separated by one extra packet to eliminate the stall. Patch by Ikhlas Ajbar. llvm-svn: 301954
* [Hexagon] Remove unused validSubtarget TSFlagsKrzysztof Parzyszek2017-05-021-5/+0
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301952
* [Hexagon] Pick a dot-old instruction that matches the architectureKrzysztof Parzyszek2017-03-061-2/+23
| | | | llvm-svn: 297031
* Make TargetInstrInfo::isPredicable take a const reference, NFCKrzysztof Parzyszek2017-03-031-1/+1
| | | | llvm-svn: 296901
* [Hexagon] Pick the right branch opcode depending on branch probabilitiesKrzysztof Parzyszek2017-03-021-15/+69
| | | | | | | Specifically, pick the opcode with the correct branch prediction, i.e. jump:t or jump:nt. llvm-svn: 296821
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-171-4/+16
| | | | | | Reapply r295371 with a fix for the Windows bot failures. llvm-svn: 295504
* Revert "[Hexagon] Start using regmasks on calls"Rafael Espindola2017-02-171-16/+4
| | | | | | | | | | This reverts commit r295371. It broke windows bots: http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio llvm-svn: 295402
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-161-4/+16
| | | | | | All the cool targets are doing it... llvm-svn: 295371
* [Hexagon] Remove leftover debugging codeKrzysztof Parzyszek2017-02-141-4/+0
| | | | llvm-svn: 295078
* [Hexagon] Replace instruction definitions with auto-generated onesKrzysztof Parzyszek2017-02-101-1/+3
| | | | llvm-svn: 294753
* [Hexagon] Fix insertBranch for loops with multiple ENDLOOP instructionsKrzysztof Parzyszek2017-02-021-18/+24
| | | | llvm-svn: 293925
* [Hexagon] Rename TypeCOMPOUND to TypeCJKrzysztof Parzyszek2017-02-021-1/+1
| | | | llvm-svn: 293894
* [CodeGen] Rename MachineInstrBuilder::addOperand. NFCDiana Picus2017-01-131-26/+24
| | | | | | | | | | | Rename from addOperand to just add, to match the other method that has been added to MachineInstrBuilder for adding more than just 1 operand. See https://reviews.llvm.org/D28057 for the whole discussion. Differential Revision: https://reviews.llvm.org/D28556 llvm-svn: 291891
* [Hexagon, TableGen] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-01-041-156/+25
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 290925
* Fix spelling mistakes in Hexagon target comments. NFC.Simon Pilgrim2016-11-171-2/+2
| | | | | | Identified by Pedro Giffuni in PR27636. llvm-svn: 287248
* [Hexagon] Remove unsafe load instructions that affect Stack Slot ColoringSumanth Gundapaneni2016-11-141-12/+0
| | | | | | | | | | | | | | | | | The Stack slot coloring pass removes a store that is followed by a load that deal with the same stack slot. The function isLoadFromStackSlot is supposed to consider the loads that have no side-effects. This patch fixed the issue by removing the unsafe loads from this function Eg: %vreg0<def> = L2_loadruh_io <fi#15>, 0 S2_storeri_io <fi#15>, 0, %vreg0 In this case, we load an unsigned extended half word and store this in to the same stack slot. The Stack slot coloring pass considers safe to remove the store. This patch marked all the non-vector byte and half word loads as unsafe. llvm-svn: 286843
* [Hexagon] Separate Hexagon subreg indices for different register classesKrzysztof Parzyszek2016-11-091-36/+40
| | | | | | | | | | | For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
* [Hexagon] Eliminate Insert4 pseudo-instruction, use combines insteadKrzysztof Parzyszek2016-11-091-42/+0
| | | | llvm-svn: 286368
* MachineInstrBundle: Pass iterators to getBundle(Start|End); NFCMatthias Braun2016-10-251-1/+1
| | | | | | | | This is a function to go backwards in a block to find the first instruction in a bundle, so iterator is a more natural choice for parameter/return rather than a reference to a MachineInstruction. llvm-svn: 285051
* Use StringRef instead of raw pointers in MCAsmInfo/MCInstrInfo APIs (NFC)Mehdi Amini2016-10-011-2/+2
| | | | llvm-svn: 283018
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