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* [Hexagon] Use integer instructions for floating point immediatesKrzysztof Parzyszek2016-08-101-1/+1
| | | | | | | | | | | | Floating point instructions use general purpose registers, so the few instructions that can put floating point immediates into registers are, in fact, integer instruction. Use them explicitly instead of having pseudo-instructions specifically for dealing with floating point values. Simplify the constant loading instructions (from sdata) to have only two: one for 32-bit values and one for 64-bit values: CONST32 and CONST64. llvm-svn: 278244
* [Hexagon] Check for offset overflow when reserving scavenging slotsKrzysztof Parzyszek2016-08-011-1/+14
| | | | | | | | | Scavenging slots were only reserved when pseudo-instruction expansion in frame lowering created new virtual registers. It is possible to still need a scavenging slot even if no virtual registers were created, in cases where the stack is large enough to overflow instruction offsets. llvm-svn: 277355
* [Hexagon] Referencify MachineInstr in HexagonInstrInfo, NFCKrzysztof Parzyszek2016-07-291-22/+22
| | | | llvm-svn: 277220
* [Hexagon] Insert CFI instructions before throwing callsKrzysztof Parzyszek2016-07-281-20/+31
| | | | | | | | Normally, CFI instructions should be inserted after allocframe, but if allocframe is in the same packet with a call, the CFI instructions should be inserted before that packet. llvm-svn: 277020
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-41/+41
| | | | | | | getFrameInfo() never returns nullptr so we should use a reference instead of a pointer. llvm-svn: 277017
* [Hexagon] Add option to bisect spill slot optimizationKrzysztof Parzyszek2016-07-271-2/+17
| | | | llvm-svn: 276917
* [Hexagon] Do not optimize volatile stack spill slotsKrzysztof Parzyszek2016-07-271-22/+11
| | | | llvm-svn: 276916
* [Hexagon] Handle extended versions of restore routinesKrzysztof Parzyszek2016-07-271-2/+11
| | | | llvm-svn: 276903
* [Hexagon] Add saved callee-saved registers as live-in in non-wrapped blocksKrzysztof Parzyszek2016-07-271-7/+26
| | | | | | | | | | | | | The callee-saved registers that are saved in a function are not pristine, and so they can be defined and used. In case of shrink-wrapping though, there are blocks that are outside of the save/restore range, and in those blocks the saved registers must be treated as pristine. To avoid any uses of these registers, add them as live-in in all those blocks. This was already done for blocks reaching function exits after restore, add code that does the same for blocks reached from the function entry before save. llvm-svn: 276886
* [Hexagon] Add target feature to generate long callsKrzysztof Parzyszek2016-07-251-17/+45
| | | | llvm-svn: 276638
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-301-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. llvm-svn: 274189
* Use isPositionIndependent in a few more places.Rafael Espindola2016-06-281-2/+2
| | | | | | | | | I think this converts all the simple cases that really just care about the generated code being position independent or not. The remaining uses are a bit more complicated and are checking things like "is this a library or executable" or "can this symbol be preempted". llvm-svn: 274055
* Run clang-tidy's performance-unnecessary-copy-initialization over LLVM.Benjamin Kramer2016-06-121-1/+1
| | | | | | No functionality change intended. llvm-svn: 272516
* Apply clang-tidy's misc-static-assert where it makes sense.Benjamin Kramer2016-05-271-2/+2
| | | | | | | Also fold conditions into assert(0) where it makes sense. No functional change intended. llvm-svn: 270982
* [Hexagon] Enable the post-RA schedulerKrzysztof Parzyszek2016-05-261-7/+88
| | | | | | | | | The aggressive anti-dependency breaker can rename the restored callee- saved registers. To prevent this, mark these registers are live on all paths to the return/tail-call instructions, and add implicit use operands for them to these instructions. llvm-svn: 270898
* [Hexagon] Make getCallerSavedRegs specific to a register classKrzysztof Parzyszek2016-05-161-18/+17
| | | | llvm-svn: 269674
* [Hexagon] Use offsets relative to FP+8 in .cfi_offset instructionsKrzysztof Parzyszek2016-05-111-5/+19
| | | | | | | | When generating .cfi_offset instructions, make sure that the offset is calculated with respect to the register used to define the CFA (which is currently always FP+8). llvm-svn: 269191
* [Hexagon] Register save/restore functions do not follow regular conventionsKrzysztof Parzyszek2016-04-251-22/+24
| | | | | | Do not mark them as modifying any of the volatile registers by default. llvm-svn: 267433
* Add MachineFunctionProperty checks for AllVRegsAllocated for target passesDerek Schuff2016-04-041-0/+4
| | | | | | | | | | | | | | Summary: This adds the same checks that were added in r264593 to all target-specific passes that run after register allocation. Reviewers: qcolombet Subscribers: jyknight, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18525 llvm-svn: 265313
* Change eliminateCallFramePseudoInstr() to return an iteratorHans Wennborg2016-03-311-4/+4
| | | | | | | | | | | | | | | | | | | | | This will become necessary in a subsequent change to make this method merge adjacent stack adjustments, i.e. it might erase the previous and/or next instruction. It also greatly simplifies the calls to this function from Prolog- EpilogInserter. Previously, that had a bunch of logic to resume iteration after the call; now it just continues with the returned iterator. Note that this changes the behaviour of PEI a little. Previously, it attempted to re-visit the new instruction created by eliminateCallFramePseudoInstr(). That code was added in r36625, but I can't see any reason for it: the new instructions will obviously not be pseudo instructions, they will not have FrameIndex operands, and we have already accounted for the stack adjustment. Differential Revision: http://reviews.llvm.org/D18627 llvm-svn: 265036
* [Hexagon] Improve handling of unaligned vector loads and storesKrzysztof Parzyszek2016-03-281-5/+7
| | | | llvm-svn: 264584
* [Hexagon] Only use restore functions for single register at -OzKrzysztof Parzyszek2016-03-281-0/+11
| | | | llvm-svn: 264581
* [Hexagon] Speed up frame lowering when no optimizations are enabledKrzysztof Parzyszek2016-03-281-16/+24
| | | | | | | | - Do not optimize stack slots in optnone functions. - Get aligned-base register from HexagonMachineFunctionInfo instead of looking for ALIGNA instruction in the function's body. llvm-svn: 264580
* [Hexagon] Be sure to treat subregisters of a CSR as CSRs as wellKrzysztof Parzyszek2016-03-241-5/+8
| | | | llvm-svn: 264331
* [Hexagon] Add support for run-time stack overflow checkingKrzysztof Parzyszek2016-03-241-11/+45
| | | | | | Patch by Sundeep Kushwaha. llvm-svn: 264328
* [Hexagon] Generate PIC-specific versions of save/restore routinesKrzysztof Parzyszek2016-03-241-5/+17
| | | | | | | | | | | | In PIC mode, the registers R14, R15 and R28 are reserved for use by the PLT handling code. This causes all functions to clobber these registers. While this is not new for regular function calls, it does also apply to save/restore functions, which do not follow the standard ABI conventions with respect to the volatile/non-volatile registers. Patch by Jyotsna Verma. llvm-svn: 264324
* [Hexagon] Fix reserving emergency spill slots for register scavengerKrzysztof Parzyszek2016-03-211-18/+11
| | | | | | | - R10 and R11 are not reserved registers. - Check for reserved registers when finding unused caller-saved registers. llvm-svn: 263977
* CodeGen: Change MachineInstr to use MachineInstr&, NFCDuncan P. N. Exon Smith2016-02-271-2/+2
| | | | | | | | Change MachineInstr API to prefer MachineInstr& over MachineInstr* whenever the parameter is expected to be non-null. Slowly inching toward being able to fix PR26753. llvm-svn: 262149
* CodeGen: TII: Take MachineInstr& in predicate API, NFCDuncan P. N. Exon Smith2016-02-231-2/+2
| | | | | | | | | | | | | Change TargetInstrInfo API to take `MachineInstr&` instead of `MachineInstr*` in the functions related to predicated instructions (I'll try to come back later and get some of the rest). All of these functions require non-null parameters already, so references are more clear. As a bonus, this happens to factor away a host of implicit iterator => pointer conversions. No functionality change intended. llvm-svn: 261605
* CodeGen: Bring back MachineBasicBlock::iterator::getInstrIterator()...Duncan P. N. Exon Smith2016-02-221-1/+1
| | | | | | | | | | | | | | | | | | This is a little embarrassing. When I reverted r261504 (getIterator() => getInstrIterator()) in r261567, I did a `git grep` to see if there were new calls to `getInstrIterator()` that I needed to migrate. There were 10-20 hits, and I blindly did a `sed ...` before calling `ninja check`. However, these were `MachineInstrBundleIterator::getInstrIterator()`, which predated r261567. Perhaps coincidentally, these had an identical name and return type. This commit undoes my careless sed and restores `MachineBasicBlock::iterator::getInstrIterator()`. llvm-svn: 261577
* Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC"Duncan P. N. Exon Smith2016-02-221-1/+1
| | | | | | | | | | This reverts commit r261504, since it's not obvious the new name is better: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160222/334298.html I'll recommit if we get consensus that it's the right direction. llvm-svn: 261567
* [Hexagon] Fold object construction into map::insertKrzysztof Parzyszek2016-02-171-2/+2
| | | | llvm-svn: 261096
* [Hexagon] Replace use of "std::map::emplace" with "insert"Krzysztof Parzyszek2016-02-131-1/+4
| | | | | | | Gcc 4.7.2-4 does not seem to have "emplace" in its implementation of map. This should fix the build failure on polly-amd64-linux. llvm-svn: 260816
* HexagonFrameLowering.cpp: Appease msc18 to give an explicit constructor ↵NAKAMURA Takumi2016-02-131-2/+4
| | | | | | SlotInfo() instead of member initializers. llvm-svn: 260812
* [Hexagon] Optimize stack slot spillsKrzysztof Parzyszek2016-02-121-3/+356
| | | | | | | | | | | | | | Replace spills to memory with spills to registers, if possible. This applies mostly to predicate registers (both scalar and vector), since they are very limited in number. A spill of a predicate register may happen even if there is a general-purpose register available. In cases like this the stack spill/reload may be eliminated completely. This optimization will consider all stack objects, regardless of where they came from and try to match the live range of the stack slot with a dead range of a register from an appropriate register class. llvm-svn: 260758
* [Hexagon] Replace expansion of spill pseudo-instructions in frame loweringKrzysztof Parzyszek2016-02-121-314/+441
| | | | | | | | | Rewrite the code to handle all pseudo-instructions in a single pass. This temporarily reverts spill slot optimization that used general- purpose registers to hold values of spilled predicate registers. llvm-svn: 260696
* [Hexagon] Use general purpose registers to spill pred/mod registers intoKrzysztof Parzyszek2016-01-221-71/+282
| | | | | | Patch by Tobias Edler Von Koch. llvm-svn: 258527
* Update to use new name alignTo().Rui Ueyama2016-01-141-2/+2
| | | | llvm-svn: 257804
* Hexagon: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-201-1/+1
| | | | | | | | | | | | | | | | | | | There are two things out of the ordinary in this commit. First, I made a loop obviously "infinite" in HexagonInstrInfo.cpp. After checking if an instruction was at the beginning of a basic block (in which case, `break`), the loop decremented and checked the iterator for `nullptr` as the loop condition. This has never been possible (the prev pointers are always been circular, so even with the weird ilist/iplist implementation, this isn't been possible), so I removed the condition. Second, in HexagonAsmPrinter.cpp there was another case of comparing a `MachineBasicBlock::instr_iterator` against `MachineBasicBlock::end()` (which returns `MachineBasicBlock::iterator`). While not incorrect, it's fragile. I switched this to `::instr_end()`. All that said, no functionality change intended here. llvm-svn: 250778
* [Hexagon] Fix debug information for local objectsKrzysztof Parzyszek2015-10-191-46/+151
| | | | | | | | | | | | - Isolate the check for the existence of a stack frame into hasFP. - Implement getFrameIndexReference for DWARF address computation. - Use getFrameIndexReference for offset computation in eliminateFrameIndex. - Preserve debug information for dynamically allocated stack objects. - Prefer FP to access local objects at -O0. - Add experimental code to skip allocframe when not strictly necessary (disabled by default). llvm-svn: 250718
* [Hexagon] Delay emission of CFI instructionsKrzysztof Parzyszek2015-10-191-97/+169
| | | | | | | Emit the CFI instructions after all code transformation have been done. This will avoid any interference between CFI instructions and packetization. llvm-svn: 250714
* MachineBasicBlock: Factor out common code into isReturnBlock()Matthias Braun2015-09-251-2/+2
| | | | llvm-svn: 248617
* Remove redundant TargetFrameLowering::getFrameIndexOffset virtualJames Y Knight2015-08-151-4/+14
| | | | | | | | | | | function. This was the same as getFrameIndexReference, but without the FrameReg output. Differential Revision: http://reviews.llvm.org/D12042 llvm-svn: 245148
* wrap OptSize and MinSize attributes for easier and consistent access (NFCI)Sanjay Patel2015-08-041-2/+2
| | | | | | | | | | | | | | | | | Create wrapper methods in the Function class for the OptimizeForSize and MinSize attributes. We want to hide the logic of "or'ing" them together when optimizing just for size (-Os). Currently, we are not consistent about this and rely on a front-end to always set OptimizeForSize (-Os) if MinSize (-Oz) is on. Thus, there are 18 FIXME changes here that should be added as follow-on patches with regression tests. This patch is NFC-intended: it just replaces existing direct accesses of the attributes by the equivalent wrapper call. Differential Revision: http://reviews.llvm.org/D11734 llvm-svn: 243994
* MachineRegisterInfo: Remove UsedPhysReg infrastructureMatthias Braun2015-07-141-2/+2
| | | | | | | | | | | | | We have a detailed def/use lists for every physical register in MachineRegisterInfo anyway, so there is little use in maintaining an additional bitset of which ones are used. Removing it frees us from extra book keeping. This simplifies VirtRegMap. Differential Revision: http://reviews.llvm.org/D10911 llvm-svn: 242173
* PrologEpilogInserter: Rewrite API to determine callee save regsiters.Matthias Braun2015-07-141-5/+6
| | | | | | | | | | | | | | | | This changes TargetFrameLowering::processFunctionBeforeCalleeSavedScan(): - Rename the function to determineCalleeSaves() - Pass a bitset of callee saved registers by reference, thus avoiding the function-global PhysRegUsed bitset in MachineRegisterInfo. - Without PhysRegUsed the implementation is fine tuned to not save physcial registers which are only read but never modified. Related to rdar://21539507 Differential Revision: http://reviews.llvm.org/D10909 llvm-svn: 242165
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-1/+1
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-1/+1
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* CodeGen: Use mop_iterator instead of MIOperands/ConstMIOperandsMatthias Braun2015-05-291-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | MIOperands/ConstMIOperands are classes iterating over the MachineOperand of a MachineInstr, however MachineInstr::mop_iterator does the same thing. I assume these two iterators exist to have a uniform interface to iterate over the operands of a machine instruction bundle and a single machine instruction. However in practice I find it more confusing to have 2 different iterator classes, so this patch transforms (nearly all) the code to use mop_iterators. The only exception being MIOperands::anlayzePhysReg() and MIOperands::analyzeVirtReg() still needing an equivalent, I leave that as an exercise for the next patch. Differential Revision: http://reviews.llvm.org/D9932 This version is slightly modified from the proposed revision in that it introduces MachineInstr::getOperandNo to avoid the extra counting variable in the few loops that previously used MIOperands::getOperandNo. llvm-svn: 238539
* MC: Clean up method names in MCContext.Jim Grosbach2015-05-181-1/+1
| | | | | | | The naming was a mish-mash of old and new style. Update to be consistent with the new. NFC. llvm-svn: 237594
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