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* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-24/+31
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [LivePhysRegs] Remove registers clobbered by regmasks from the live setKrzysztof Parzyszek2018-04-301-5/+0
| | | | | | | | Dead defs were being removed from the live set (in stepForward), but registers clobbered by regmasks weren't (more specifically, they were actually removed by removeRegsInMask, but then they were added back in). llvm-svn: 331219
* [Hexagon] Add support for "new" circular buffer intrinsicsKrzysztof Parzyszek2018-03-281-2/+2
| | | | | | | | | | | | | | | | | | | These instructions have been around for a long time, but we haven't supported intrinsics for them. The "new" versions use the CSx register for the start of the buffer instead of the K field in the Mx register. We need to use pseudo instructions for these instructions until after register allocation. The problem is that these instructions allocate a M0/CS0 or M1/CS1 pair. But, we can't generate code for the CSx set-up until after register allocation when the Mx register has been fixed for the instruction. There is a related clang patch. Patch by Brendon Cahoon. llvm-svn: 328724
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-02-221-1/+1
| | | | | | "a a" -> "a" llvm-svn: 325752
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-7/+6
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* [Hexagon] Add support for Hexagon V65Krzysztof Parzyszek2017-12-111-3/+16
| | | | llvm-svn: 320404
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-11/+16
| | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
* [CodeGen] Rename functions PrintReg* to printReg*Francis Visoiu Mistrih2017-11-281-5/+5
| | | | | | | | | | | LLVM Coding Standards: Function names should be verb phrases (as they represent actions), and command-like function should be imperative. The name should be camel case, and start with a lower case letter (e.g. openFile() or isFoo()). Differential Revision: https://reviews.llvm.org/D40416 llvm-svn: 319168
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-151-87/+30
| | | | | | | This removes the duplicate HVX instruction set for the 128-byte mode. Single instruction set now works for both modes (64- and 128-byte). llvm-svn: 313362
* [Hexagon] Make getMemAccessSize return size in bytesKrzysztof Parzyszek2017-09-141-2/+2
| | | | | | | | It used to return the actual field value from the instruction descriptor. There is no reason for that, that value is not interesting in any way and the specifics of its encoding in the descriptor should not be exposed. llvm-svn: 313257
* [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-07-261-10/+14
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 309230
* [NFC] Move DEBUG_TYPE below includes in HexagonJakub Kuderski2017-07-131-2/+2
| | | | llvm-svn: 307947
* [Hexagon] Do not rely on callee-saved info in hasFPKrzysztof Parzyszek2017-07-111-12/+2
| | | | llvm-svn: 307675
* [Hexagon] Implement frame pointer elimination with -fomit-frame-pointerKrzysztof Parzyszek2017-06-301-75/+106
| | | | | | | It applies to leaf functions that are otherwise not required to have a frame pointer. llvm-svn: 306888
* [Hexagon] Handle cases when the aligned stack pointer is missingKrzysztof Parzyszek2017-06-261-1/+17
| | | | llvm-svn: 306288
* Revert "[Hexagon] Handle decreasing of stack alignment in frame lowering"Krzysztof Parzyszek2017-06-231-17/+2
| | | | | | This breaks passing of aligned function arguments. llvm-svn: 306145
* [Hexagon] Handle decreasing of stack alignment in frame loweringKrzysztof Parzyszek2017-06-231-2/+17
| | | | llvm-svn: 306124
* [Hexagon] Recognize potential offset overflow for store-imm to stackKrzysztof Parzyszek2017-06-221-4/+39
| | | | | | | Reserve an extra scavenging stack slot if the offset field in store- -immediate instructions may overflow. llvm-svn: 306004
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
* LivePhysRegs: Rework constructor + documentation; NFCMatthias Braun2017-05-261-1/+1
| | | | | | | - Take reference instead of pointer to a TRI that cannot be nullptr. - Improve documentation comments. llvm-svn: 304038
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-21/+22
| | | | | | | | | | | | | | | 1. RegisterClass::getSize() is split into two functions: - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const; - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const; 2. RegisterClass::getAlignment() is replaced by: - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const; This will allow making those values depend on subtarget features in the future. Differential Revision: https://reviews.llvm.org/D31783 llvm-svn: 301221
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-171-10/+24
| | | | | | Reapply r295371 with a fix for the Windows bot failures. llvm-svn: 295504
* Revert "[Hexagon] Start using regmasks on calls"Rafael Espindola2017-02-171-24/+10
| | | | | | | | | | This reverts commit r295371. It broke windows bots: http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio llvm-svn: 295402
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-161-10/+24
| | | | | | All the cool targets are doing it... llvm-svn: 295371
* [Hexagon] Remove dead defs from the live set when expanding wstoresKrzysztof Parzyszek2017-01-181-1/+8
| | | | llvm-svn: 292445
* Remove unused lambda captures. NFCMalcolm Parsons2017-01-131-3/+3
| | | | llvm-svn: 291916
* [CodeGen] Rename MachineInstrBuilder::addOperand. NFCDiana Picus2017-01-131-3/+2
| | | | | | | | | | | Rename from addOperand to just add, to match the other method that has been added to MachineInstrBuilder for adding more than just 1 operand. See https://reviews.llvm.org/D28057 for the whole discussion. Differential Revision: https://reviews.llvm.org/D28556 llvm-svn: 291891
* [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2016-12-161-78/+79
| | | | | | other minor fixes (NFC). llvm-svn: 289907
* Move FrameInstructions from MachineModuleInfo to MachineFunctionMatthias Braun2016-11-301-6/+6
| | | | | | | | | | | This is per function data so it is better kept at the function instead of the module. This is a necessary step to have machine module passes work properly. Differential Revision: https://reviews.llvm.org/D27185 llvm-svn: 288291
* [Hexagon] Separate Hexagon subreg indices for different register classesKrzysztof Parzyszek2016-11-091-6/+6
| | | | | | | | | | | For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
* [Hexagon] Handle spills of partially defined double vector registersKrzysztof Parzyszek2016-10-211-21/+36
| | | | | | | | | | | | After register allocation it is possible to have a spill of a register that is only partially defined. That in itself it fine, but creates a problem for double vector registers. Stores of such registers are pseudo instructions that are expanded into pairs of individual vector stores, and in case of a partially defined source, one of the stores may use an entirely undefined register. To avoid this, track the defined parts and only generate actual stores for those. llvm-svn: 284841
* Use __func__ directly now that all supported compilers support itReid Kleckner2016-10-201-1/+1
| | | | | | Remove the portability macro now that it is unused. llvm-svn: 284681
* MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, ↵Matthias Braun2016-08-251-1/+1
| | | | | | | | | | | | | compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
* [Hexagon] Do not cache alloca instructions during iselKrzysztof Parzyszek2016-08-191-2/+5
| | | | | | | | They can be deleted or replicated, so the cache may become outdated. They only need to be visited once during frame lowering, so just scan the function instead. llvm-svn: 279297
* [Hexagon] Standardize next batch of pseudo instructionsKrzysztof Parzyszek2016-08-161-11/+11
| | | | | | | | | | | | | ALIGNA PS_aligna ALLOCA PS_alloca TFR_FI PS_fi TFR_FIA PS_fia TFR_PdFalse PS_false TFR_PdTrue PS_true VMULW PS_vmulw VMULW_ACC PS_vmulw_acc llvm-svn: 278832
* [Hexagon] Standardize vector predicate load/store pseudo instructionsKrzysztof Parzyszek2016-08-161-4/+4
| | | | | | | | | | | | - Remove unused instructions: LDriq_pred_vec_V6, STriq_pred_vec_V6, and the 128B counterparts. - Rename: LDriq_pred_V6 PS_vloadrq_ai LDriq_pred_V6_128B PS_vloadrq_ai_128B STriq_pred_V6 PS_vstorerq_ai STriq_pred_V6_128B PS_vstorerq_ai_128B llvm-svn: 278813
* [Hexagon] Cleanup and standardize vector load/store pseudo instructionsKrzysztof Parzyszek2016-08-121-32/+32
| | | | | | | | | | | | | | | | | | | | Remove the following single-vector load/store pseudo instructions, use real instructions instead: LDriv_pseudo_V6 STriv_pseudo_V6 LDriv_pseudo_V6_128B STriv_pseudo_V6_128B LDrivv_indexed STrivv_indexed LDrivv_indexed_128B STrivv_indexed_128B Rename the double-vector load/store pseudo instructions, add unaligned counterparts: -- old -- -- new -- -- unaligned -- LDrivv_pseudo_V6 PS_vloadrw_io PS_vloadrwu_io LDrivv_pseudo_V6_128B PS_vloadrw_io_128B PS_vloadrwu_io_128B STrivv_pseudo_V6 PS_vstorerw_io PS_vstorerwu_io STrivv_pseudo_V6_128B PS_vstorerw_io_128 PS_vstorerwu_io_128 llvm-svn: 278564
* [Hexagon] Standardize pseudo-instructions for calls and returnsKrzysztof Parzyszek2016-08-121-5/+5
| | | | | | | | | | | | | | | | | | | - CALLv3nr PS_call_nr - CALLRv3nr PS_callr_nr - CALLstk PS_call_stk - TCRETURNi PS_tailcall_i - TCRETURNr PS_tailcall_r - JMPret PS_jmpret - JMPrett PS_jmprett - JMPretf PS_jmpretf - JMPrettnew PS_jmprettnew - JMPretfnew PS_jmpretfnew - JMPrettnewpt PS_jmprettnewpt - JMPretfnewpt PS_jmpretfnewpt llvm-svn: 278499
* Use the range variant of find_if instead of unpacking begin/endDavid Majnemer2016-08-121-1/+1
| | | | | | No functionality change is intended. llvm-svn: 278443
* [Hexagon] Use integer instructions for floating point immediatesKrzysztof Parzyszek2016-08-101-1/+1
| | | | | | | | | | | | Floating point instructions use general purpose registers, so the few instructions that can put floating point immediates into registers are, in fact, integer instruction. Use them explicitly instead of having pseudo-instructions specifically for dealing with floating point values. Simplify the constant loading instructions (from sdata) to have only two: one for 32-bit values and one for 64-bit values: CONST32 and CONST64. llvm-svn: 278244
* [Hexagon] Check for offset overflow when reserving scavenging slotsKrzysztof Parzyszek2016-08-011-1/+14
| | | | | | | | | Scavenging slots were only reserved when pseudo-instruction expansion in frame lowering created new virtual registers. It is possible to still need a scavenging slot even if no virtual registers were created, in cases where the stack is large enough to overflow instruction offsets. llvm-svn: 277355
* [Hexagon] Referencify MachineInstr in HexagonInstrInfo, NFCKrzysztof Parzyszek2016-07-291-22/+22
| | | | llvm-svn: 277220
* [Hexagon] Insert CFI instructions before throwing callsKrzysztof Parzyszek2016-07-281-20/+31
| | | | | | | | Normally, CFI instructions should be inserted after allocframe, but if allocframe is in the same packet with a call, the CFI instructions should be inserted before that packet. llvm-svn: 277020
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-41/+41
| | | | | | | getFrameInfo() never returns nullptr so we should use a reference instead of a pointer. llvm-svn: 277017
* [Hexagon] Add option to bisect spill slot optimizationKrzysztof Parzyszek2016-07-271-2/+17
| | | | llvm-svn: 276917
* [Hexagon] Do not optimize volatile stack spill slotsKrzysztof Parzyszek2016-07-271-22/+11
| | | | llvm-svn: 276916
* [Hexagon] Handle extended versions of restore routinesKrzysztof Parzyszek2016-07-271-2/+11
| | | | llvm-svn: 276903
* [Hexagon] Add saved callee-saved registers as live-in in non-wrapped blocksKrzysztof Parzyszek2016-07-271-7/+26
| | | | | | | | | | | | | The callee-saved registers that are saved in a function are not pristine, and so they can be defined and used. In case of shrink-wrapping though, there are blocks that are outside of the save/restore range, and in those blocks the saved registers must be treated as pristine. To avoid any uses of these registers, add them as live-in in all those blocks. This was already done for blocks reaching function exits after restore, add code that does the same for blocks reached from the function entry before save. llvm-svn: 276886
* [Hexagon] Add target feature to generate long callsKrzysztof Parzyszek2016-07-251-17/+45
| | | | llvm-svn: 276638
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