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path: root/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
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* Move Object format code to lib/BinaryFormat.Zachary Turner2017-06-071-1/+1
| | | | | | | | | | | | This creates a new library called BinaryFormat that has all of the headers from llvm/Support containing structure and layout definitions for various types of binary formats like dwarf, coff, elf, etc as well as the code for identifying a file from its magic. Differential Revision: https://reviews.llvm.org/D33843 llvm-svn: 304864
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
* [Hexagon] Change iconst to emit 27bit relocationKrzysztof Parzyszek2017-05-021-1/+1
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301956
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-3/+3
| | | | | | | | | | | | | | | 1. RegisterClass::getSize() is split into two functions: - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const; - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const; 2. RegisterClass::getAlignment() is replaced by: - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const; This will allow making those values depend on subtarget features in the future. Differential Revision: https://reviews.llvm.org/D31783 llvm-svn: 301221
* [Hexagon] Change the vector scaling for vector offsetsKrzysztof Parzyszek2017-04-061-0/+199
| | | | | | | Keep full offset value on MI-level instructions, but have it scaled down in the MC-level instructions. llvm-svn: 299664
* [Hexagon] Remove unused variablesKrzysztof Parzyszek2017-03-311-5/+1
| | | | | | Found by PVS-Studio. Fixes llvm.org/PR31676. llvm-svn: 299262
* [Hexagon] Remove encoding bits from mapped instructionsKrzysztof Parzyszek2017-02-071-0/+33
| | | | | | | | | | - Map A2_zxtb to A2_andir. - Map PS_call_nr J2_call. - Map A2_tfr[t|f][new] to A2_padd[t|f][new]. Patch by Colin LeMahieu. llvm-svn: 294320
* [Hexagon] Separate Hexagon subreg indices for different register classesKrzysztof Parzyszek2016-11-091-10/+10
| | | | | | | | | | | For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
* Move the global variables representing each Target behind accessor functionMehdi Amini2016-10-091-1/+1
| | | | | | | | This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
* [Hexagon] Fix indentation, NFCKrzysztof Parzyszek2016-08-191-3/+3
| | | | llvm-svn: 279245
* [Hexagon] Clean up some miscellaneous V60 intrinsics a bitKrzysztof Parzyszek2016-08-161-2/+2
| | | | llvm-svn: 278823
* [Hexagon] Use integer instructions for floating point immediatesKrzysztof Parzyszek2016-08-101-19/+1
| | | | | | | | | | | | Floating point instructions use general purpose registers, so the few instructions that can put floating point immediates into registers are, in fact, integer instruction. Use them explicitly instead of having pseudo-instructions specifically for dealing with floating point values. Simplify the constant loading instructions (from sdata) to have only two: one for 32-bit values and one for 64-bit values: CONST32 and CONST64. llvm-svn: 278244
* [Hexagon] Remove unneeded/unused ISD opcodes ARGEXTEND and FCONST32Krzysztof Parzyszek2016-08-101-1/+0
| | | | llvm-svn: 278236
* [Hexagon] Add support for proper handling of H and L constraintsKrzysztof Parzyszek2016-07-261-8/+16
| | | | | | | | | H -> High part of reg pair. L -> Low part of reg pair. Patch by Sundeep Kushwaha. llvm-svn: 276773
* [NFC] Header cleanupMehdi Amini2016-04-181-3/+0
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC"Duncan P. N. Exon Smith2016-02-221-1/+1
| | | | | | | | | | This reverts commit r261504, since it's not obvious the new name is better: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160222/334298.html I'll recommit if we get consensus that it's the right direction. llvm-svn: 261567
* CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFCDuncan P. N. Exon Smith2016-02-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Delete MachineInstr::getIterator(), since the term "iterator" is overloaded when talking about MachineInstr. - Downcast to ilist_node in iplist::getNextNode() and getPrevNode() so that ilist_node::getIterator() is still available. - Add it back as MachineInstr::getInstrIterator(). This matches the naming in MachineBasicBlock. - Add MachineInstr::getBundleIterator(). This is explicitly called "bundle" (not matching MachineBasicBlock) to disintinguish it clearly from ilist_node::getIterator(). - Update all calls. Some of these I switched to `auto` to remove boiler-plate, since the new name is clear about the type. There was one call I updated that looked fishy, but it wasn't clear what the right answer was. This was in X86FrameLowering::inlineStackProbe(), added in r252578 in lib/Target/X86/X86FrameLowering.cpp. I opted to leave the behaviour unchanged, but I'll reply to the original commit on the list in a moment. llvm-svn: 261504
* [Hexagon] Adding relocation for code size, cold path optimization allowing a ↵Colin LeMahieu2016-02-161-0/+13
| | | | | | | | | | | | 23-bit 4-byte aligned relocation to be a valid instruction encoding. The usual way to get a 32-bit relocation is to use a constant extender which doubles the size of the instruction, 4 bytes to 8 bytes. Another way is to put a .word32 and mix code and data within a function. The disadvantage is it's not a valid instruction encoding and jumping over it causes prefetch stalls inside the hardware. This relocation packs a 23-bit value in to an "r0 = add(rX, #a)" instruction by overwriting the source register bits. Since r0 is the return value register, if this instruction is placed after a function call which return void, r0 will be filled with an undefined value, the prefetch won't be confused, and the callee can access the constant value by way of the link register. llvm-svn: 261006
* [NFC] Fixing naming convention, lowercase start of function name.Colin LeMahieu2016-02-151-7/+7
| | | | llvm-svn: 260903
* [Hexagon] Wrapping all MCExprs inside MCOperands within HexagonMCExpr to ↵Colin LeMahieu2016-02-151-14/+21
| | | | | | simplify handling and allow flags on the expression. llvm-svn: 260902
* [Hexagon] Make helper function static. NFC.Benjamin Kramer2016-01-121-3/+3
| | | | llvm-svn: 257476
* [Hexagon] Preprocess mapped instructions before lowering to MCKrzysztof Parzyszek2015-12-151-3/+386
| | | | llvm-svn: 255653
* [Hexagon] NFC Using canonicalizePacket to compound/duplex/pad packets rather ↵Colin LeMahieu2015-12-031-17/+11
| | | | | | than doing it separately. This also ensures the integrated assembler path matches the assembly parser path. llvm-svn: 254616
* [Hexagon] Improve lowering of instructions to the MC layerKrzysztof Parzyszek2015-12-021-8/+12
| | | | | | | | | - Add extenders when necessary. - Handle some basic relocations. This should fix the failure in tools/clang/test/CodeGenCXX/crash.cpp llvm-svn: 254564
* [Hexagon] Factoring bundle creation in to a utility function.Colin LeMahieu2015-11-131-3/+1
| | | | llvm-svn: 253056
* [Hexagon] Fixing leak in padEndloop by allocating in MCContext.Colin LeMahieu2015-11-131-1/+1
| | | | llvm-svn: 253019
* Hexagon: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-201-3/+3
| | | | | | | | | | | | | | | | | | | There are two things out of the ordinary in this commit. First, I made a loop obviously "infinite" in HexagonInstrInfo.cpp. After checking if an instruction was at the beginning of a basic block (in which case, `break`), the loop decremented and checked the iterator for `nullptr` as the loop condition. This has never been possible (the prev pointers are always been circular, so even with the weird ilist/iplist implementation, this isn't been possible), so I removed the condition. Second, in HexagonAsmPrinter.cpp there was another case of comparing a `MachineBasicBlock::instr_iterator` against `MachineBasicBlock::end()` (which returns `MachineBasicBlock::iterator`). While not incorrect, it's fragile. I switched this to `::instr_end()`. All that said, no functionality change intended here. llvm-svn: 250778
* MC: Add target hook to control symbol quotingMatt Arsenault2015-06-091-3/+3
| | | | llvm-svn: 239370
* [Hexagon] Adding functionality for searching for compound instruction pairs. ↵Colin LeMahieu2015-06-081-2/+8
| | | | | | Compound instructions reduce slot resource requirements freeing those packet slots up for more instructions. llvm-svn: 239307
* [Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.Colin LeMahieu2015-06-051-2/+6
| | | | llvm-svn: 239161
* Revert r239095 incorrect test tree.Colin LeMahieu2015-06-041-6/+2
| | | | llvm-svn: 239102
* [Hexagon] Removing unused variable.Colin LeMahieu2015-06-041-1/+0
| | | | llvm-svn: 239097
* [Hexagon] Adding functionality for duplexing. Duplexing is a way to ↵Colin LeMahieu2015-06-041-2/+7
| | | | | | compress commonly used pairs of instructions in order to reduce code size. The test case duplex.ll normally would be 8 bytes, assign register to 0 and jump to link register. After duplexing this is only 4 bytes. This also tests the HexagonMCShuffler code path which is used to make sure duplexed instructions still follow slot requirements. llvm-svn: 239095
* [Hexagon] Disassembling, printing, and emitting instructions a whole-bundle ↵Colin LeMahieu2015-05-291-34/+16
| | | | | | at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch. llvm-svn: 238556
* [AsmPrinter] Make AsmPrinter's OutStreamer member a unique_ptr.Lang Hames2015-04-241-2/+2
| | | | | | | AsmPrinter owns the OutStreamer, so an owning pointer makes sense here. Using a reference for this is crufty. llvm-svn: 235752
* Remove duplicated code and consolidate initializers.Eric Christopher2015-04-091-14/+0
| | | | llvm-svn: 234525
* Replace the MCSubtargetInfo parameter with a Triple when creatingEric Christopher2015-03-311-3/+3
| | | | | | | an MCInstPrinter. Update all callers and use where we wanted a Triple previously. llvm-svn: 233648
* Remove unused Target argument from MCInstPrinter ctor functions.Eric Christopher2015-03-301-2/+1
| | | | llvm-svn: 233607
* [Hexagon] Moving remaining methods off of HexagonMCInst in to ↵Colin LeMahieu2015-02-191-9/+9
| | | | | | HexagonMCInstrInfo and eliminating HexagonMCInst class. llvm-svn: 229914
* Define a runOnMachineFunction for the Hexagon AsmPrinter andEric Christopher2015-02-031-3/+1
| | | | | | use it to initialize the subtarget. llvm-svn: 227948
* std::unique_ptrify the MCStreamer argument to createAsmPrinterDavid Blaikie2015-01-181-0/+6
| | | | llvm-svn: 226414
* [Hexagon] Converting subclass members to an implicit operand.Colin LeMahieu2014-12-031-10/+12
| | | | llvm-svn: 223264
* [Hexagon] [NFC] Renaming *packetStart to *packetBeginColin LeMahieu2014-12-031-2/+2
| | | | llvm-svn: 223243
* [Hexagon] [NFC] Merging InstPrinter directory in to MCTargetDesc since they ↵Colin LeMahieu2014-11-201-1/+1
| | | | | | have a circular dependency. llvm-svn: 222458
* [Hexagon] Reverting 220584 to address ASAN errors.Colin LeMahieu2014-11-041-5/+5
| | | | llvm-svn: 221210
* [Hexagon] Resubmission of 220427Colin LeMahieu2014-10-241-5/+5
| | | | | | | | | | | Modified library structure to deal with circular dependency between HexagonInstPrinter and HexagonMCInst. Adding encoding bits for add opcode. Adding llvm-mc tests. Removing unit tests. http://reviews.llvm.org/D5624 llvm-svn: 220584
* Revert r220427, "[Hexagon] Adding encoding bits for add opcode."NAKAMURA Takumi2014-10-231-4/+4
| | | | | | It brought cyclic dependecy between HexagonAsmPrinter and HexagonDesc. llvm-svn: 220478
* [Hexagon] Adding encoding bits for add opcode.Colin LeMahieu2014-10-221-4/+4
| | | | | | | | | Adding llvm-mc tests. Removing unit tests. http://reviews.llvm.org/D5624 llvm-svn: 220427
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-1/+1
| | | | llvm-svn: 207197
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
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