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path: root/llvm/lib/Target/Hexagon/BitTracker.h
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* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [Hexagon] Memoize instruction positions in BitTrackerKrzysztof Parzyszek2018-02-051-1/+9
| | | | llvm-svn: 324250
* BitTracker.h needs a full definition of MachineInstr, so include the ↵Benjamin Kramer2018-02-051-1/+1
| | | | | | | | | | defining file. Patch by Dean Sturtevant! Differential Revision: https://reviews.llvm.org/D42907 llvm-svn: 324245
* [Hexagon] Remove recursion in visitUsesOf, replace with use queueKrzysztof Parzyszek2017-12-151-6/+39
| | | | | | | | | | | | | | | | This is primarily to reduce stack usage, but ordering the use queue according to the position in the code (earlier instructions visited before later ones) reduces the number of unnecessary bottoms due to visiting instructions out of order, e.g. %reg1 = copy %reg0 %reg2 = copy %reg0 %reg3 = and %reg1, %reg2 Here, reg3 should be known to be same as reg0-2, but if reg3 is evaluated after reg1 is updated, but before reg2 is updated, the two inputs to the and will appear different, causing reg3 to become bottom. llvm-svn: 320866
* [Hexagon] Better determination of register classes in bit trackerKrzysztof Parzyszek2017-09-251-0/+10
| | | | | | | | | | | Add two callbacks to MachineEvaluator, so that specific implementations can specify more details about register classes: - composeWithSubRegIndex(RC,Idx), to provide the register class for a register from RC used in conjunction with a subregister index Idx. - getPhysRegBitWidth(Reg), to provide the size in bits of the given physical register. llvm-svn: 314136
* [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-07-261-10/+11
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 309230
* [Hexagon] Cache reached blocks in bit tracker instead of scanning listKrzysztof Parzyszek2017-04-191-4/+6
| | | | llvm-svn: 300701
* [Hexagon] Allow setting register in BitVal without storing into mapKrzysztof Parzyszek2017-02-231-0/+3
| | | | | | | | | | | In the bit tracker, references to other bit values in which the register is 0 are prohibited. This means that generating self-referential register cells like { w:32 [0-15]:s[0-15] [16-31]:s[15] } is impossible. In order to get a self-referential cell, it had to be stored into a map and then reloaded from it. To avoid this step, add a function that will set the register to a given value without going through the map. llvm-svn: 296025
* [Hexagon, TableGen] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-01-041-26/+27
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 290925
* [Hexagon-ish] Add function to print cell map contents in bit trackerKrzysztof Parzyszek2016-08-031-0/+2
| | | | llvm-svn: 277622
* [Hexagon] Rerun bit tracker on new instructions in RIEKrzysztof Parzyszek2016-07-261-0/+1
| | | | | | | | | | | | | | | | | | | Consider this case: vreg1 = A2_zxth vreg0 (1) ... vreg2 = A2_zxth vreg1 (2) Redundant instruction elimination could delete the instruction (1) because the user (2) only cares about the low 16 bits. Then it could delete (2) because the input is already zero-extended. The problem is that the properties allowing each individual instruction to be deleted depend on the existence of the other instruction, so either one can be deleted, but not both. The existing check for this situation in RIE was insufficient. The fix is to update all dependent cells when an instruction is removed (replaced via COPY) in RIE. llvm-svn: 276792
* Hexagon: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-121-5/+5
| | | | | | | | | | | | | | Avoid implicit iterator conversions from MachineInstrBundleIterator to MachineInstr* in the Hexagon backend, mostly by preferring MachineInstr& over MachineInstr* and switching to range-based for loops. There's a long tail of API cleanup here, but I'm planning to leave the rest to the Hexagon maintainers. HexagonInstrInfo defines many of its own predicates, and most of them still take MachineInstr*. Some of those actually check for nullptr, so I didn't feel comfortable changing them to MachineInstr& en masse. llvm-svn: 275142
* -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are ↵David Blaikie2015-08-011-7/+0
| | | | | | | | | | deprecated in C++11 Remove some unnecessary explicit special members in Hexagon that, once removed, allow the other implicit special members to be used without depending on deprecated features. llvm-svn: 243825
* [Hexagon] Use composition instead of inheritance from STL typesBenjamin Kramer2015-07-181-8/+1
| | | | | | | | The standard containers are not designed to be inherited from, as illustrated by the MSVC hacks for NodeOrdering. No functional change intended. llvm-svn: 242616
* [Hexagon] Move BitTracker into the llvm namespace and remove redundant ↵Benjamin Kramer2015-07-131-32/+26
| | | | | | | | qualifications No functional change intended. llvm-svn: 242062
* [Hexagon] Implement bit-tracking facility with specifics for HexagonKrzysztof Parzyszek2015-07-071-0/+455
This includes code that is intended to be target-independent as well as the Hexagon-specific details. This is just the framework without any users. llvm-svn: 241595
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