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* CellSPU:Scott Michel2009-01-061-15/+49
| | | | | | | | | | | | - Fix bugs 3194, 3195: i128 load/stores produce correct code (although, we need to ensure that i128 is 16-byte aligned in real life), and 128 zero- extends are supported. - New td file: SPU128InstrInfo.td: this is where all new i128 support should be put in the future. - Continue to hammer on i64 operations and test cases; ensure that the only remaining problem will be i64 mul. llvm-svn: 61784
* CellSPU:Scott Michel2009-01-031-35/+1
| | | | | | | | | - Remove custom lowering for BRCOND - Add remaining functionality for branches in SPUInstrInfo, such as branch condition reversal and load/store folding. Updated BrCond test to reflect branch reversal. llvm-svn: 61597
* Fix PR3274: when promoting the condition of a BRCOND node,Duncan Sands2009-01-011-3/+3
| | | | | | | | | | promote from i1 all the way up to the canonical SetCC type. In order to discover an appropriate type to use, pass MVT::Other to getSetCCResultType. In order to be able to do this, change getSetCCResultType to take a type as an argument, not a value (this is also more logical). llvm-svn: 61542
* - Start moving target-dependent nodes that could be represented by anScott Michel2008-12-301-351/+36
| | | | | | | | | | | | | instruction sequence and cannot ordinarily be simplified by DAGcombine into the various target description files or SPUDAGToDAGISel.cpp. This makes some 64-bit operations legal. - Eliminate target-dependent ISD enums. - Update tests. llvm-svn: 61508
* - Various '#if 0' cleanups.Scott Michel2008-12-291-61/+40
| | | | | | | | | - Move v4i32, i32 mul into SPUInstrInfo.td, with a few more instruction cleanups there as well. - Make SMUL_LOHI, UMUL_LOHI competely illegal for Cell SPU, to better assist Chris to see the problem in bug 3101. llvm-svn: 61464
* - Remove Tilmann's custom truncate lowering: it completely hosed overScott Michel2008-12-271-387/+410
| | | | | | | | | | | | | | | | | | | | | | | | DAGcombine's ability to find reasons to remove truncates when they were not needed. Consequently, the CellSPU backend would produce correct, but _really slow and horrible_, code. Replaced with instruction sequences that do the equivalent truncation in SPUInstrInfo.td. - Re-examine how unaligned loads and stores work. Generated unaligned load code has been tested on the CellSPU hardware; see the i32operations.c and i64operations.c in CodeGen/CellSPU/useful-harnesses. (While they may be toy test code, it does prove that some real world code does compile correctly.) - Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc fault because i64 ult is not yet implemented.) - Added i64 eq and neq for setcc and select/setcc; started new instruction information file for them in SPU64InstrInfo.td. Additional i64 operations should be added to this file and not to SPUInstrInfo.td. llvm-svn: 61447
* CellSPU:Scott Michel2008-12-101-8/+6
| | | | | | | | | - Fix bug 3185, with misc other cleanups. - Needed to implement SPUInstrInfo::InsertBranch(). CAUTION: Not sure what gets or needs to get passed to InsertBranch() to insert a conditional branch. This will abort for now until a good test case shows up. llvm-svn: 60811
* CellSPU:Scott Michel2008-12-091-2/+5
| | | | | | | | - Change default scheduling preference to list-burr, which produces somewhat better code than the default. Could also use list-tdrr, but need to ask dev list about the appropriate handy mnemonic before commiting. llvm-svn: 60738
* CellSPU: Fix bug 3055Scott Michel2008-12-041-22/+55
| | | | | | | | | - Add v4f32, v2f64 to LowerVECTOR_SHUFFLE - Look for vector rotate in shuffle elements, generate a vector rotate instead of a full-blown shuffle when opportunity presents itself. - Generate larger test harness and fix a few interesting but obscure bugs. llvm-svn: 60552
* Missing closing brace and reverse conditional condition on NDEBUGScott Michel2008-12-041-5/+5
| | | | llvm-svn: 60541
* This code is apparently quite confused. In the meantime,Chris Lattner2008-12-041-1/+2
| | | | | | get it building when NDEBUG is set. llvm-svn: 60532
* CellSPU:Scott Michel2008-12-041-65/+55
| | | | | | | | | | | | | | | | | | | | | | - First patch from Nehal Desai, a new contributor at Aerospace. Nehal's patch fixes sign/zero/any-extending loads for integers and floating point. Example code, compiled w/o debugging or optimization where he first noticed the bug: int main(void) { float a = 99.0; printf("%d\n", a); return 0; } Verified that this code actually works on a Cell SPU. Changes by Scott Michel: - Fix bug in the value type list constructed by SPUISD::LDRESULT to include both the load result's result and chain, not just the chain alone. - Simplify LowerLOAD and remove extraneous and unnecessary chains. - Remove unused SPUISD pseudo instructions. llvm-svn: 60526
* CellSPU:Scott Michel2008-12-021-1/+109
| | | | | | | | | | - Incorporate Tilmann Scheller's ISD::TRUNCATE custom lowering patch - Update SPU calling convention info, even if it's not used yet (but can be at some point or another) - Ensure that any-extended f32 loads are custom lowered, especially when they're promoted for use in printf. llvm-svn: 60438
* CellSPU:Scott Michel2008-12-011-37/+39
| | | | | | | | | - Fix v2[if]64 vector insertion code before IBM files a bug report. - Ensure that zero (0) offsets relative to $sp don't trip an assert (add $sp, 0 gets legalized to $sp alone, tripping an assert) - Shuffle masks passed to SPUISD::SHUFB are now v16i8 or v4i32 llvm-svn: 60358
* There are no longer any places that require aDuncan Sands2008-12-011-2/+2
| | | | | | | | MERGE_VALUES node with only one operand, so get rid of special code that only existed to handle that possibility. llvm-svn: 60349
* Change the interface to the type legalization methodDuncan Sands2008-12-011-2/+3
| | | | | | | | | | | ReplaceNodeResults: rather than returning a node which must have the same number of results as the original node (which means mucking around with MERGE_VALUES, and which is also easy to get wrong since SelectionDAG folding may mean you don't get the node you expect), return the results in a vector. llvm-svn: 60348
* CellSPU: Fix mnemonic typo in pattern; "shlqbyi" -> "shlqby".Scott Michel2008-11-251-0/+2
| | | | llvm-svn: 59998
* CellSPU:Scott Michel2008-11-241-4/+15
| | | | | | | | | (a) Slight rethink on i64 zero/sign/any extend code - use a shuffle to directly zero-extend i32 to i64, but use rotates and shifts for sign extension. Also ensure unified register consistency. (b) Add new test harness for i64 operations: i64ops.ll llvm-svn: 59970
* CellSPU:Scott Michel2008-11-241-87/+59
| | | | | | | | | | (a) Improve the extract element code: there's no need to do gymnastics with rotates into the preferred slot if a shuffle will do the same thing. (b) Rename a couple of SPUISD pseudo-instructions for readability and better semantic correspondence. (c) Fix i64 sign/any/zero extension lowering. llvm-svn: 59965
* Rename SetCCResultContents to BooleanContents. InDuncan Sands2008-11-231-1/+1
| | | | | | | practice these booleans are mostly produced by SetCC, however the concept is more general. llvm-svn: 59911
* CellSPU: Fix bug 3056. Varadic extract_element was not implemented (nor was itScott Michel2008-11-221-78/+242
| | | | | | ever conceived to occur). llvm-svn: 59891
* CellSPU:Scott Michel2008-11-211-32/+34
| | | | | | | | (a) Fix bgs 3052, 3057 (b) Incorporate Duncan's suggestions re: i1 promotion (c) Indentation updates. llvm-svn: 59790
* CellSPU:Scott Michel2008-11-201-6/+5
| | | | | | | | (a) Remove moved file (SPUAsmPrinter.cpp) to make svn happy. (b) Remove truncated stores that will never be used. (c) Add initial support for __muldi3 as a libcall. llvm-svn: 59734
* CellSPU: Custom lower truncating stores of i8 to i1 (should not have beenScott Michel2008-11-201-1/+1
| | | | | | promote), fix signed conversion of indexed offsets. llvm-svn: 59707
* CellSPU: Adjust spacing/tabulationScott Michel2008-11-201-8/+8
| | | | llvm-svn: 59703
* CellSPU: Do not custom lower i1 stores, rely on type legalization to do theScott Michel2008-11-191-34/+11
| | | | | | right thing and promote the store to i8. llvm-svn: 59648
* Temporary check-in for Duncan to demonstrate CellSPU store problem.Scott Michel2008-11-191-8/+41
| | | | llvm-svn: 59637
* Unbreak the buildbot and back out (inadvertant) casting edits in CellSPUScott Michel2008-11-111-7/+7
| | | | | | backend. llvm-svn: 59018
* CellSPU: Fix bug 3606, as well as some ongoing work.Scott Michel2008-11-101-10/+33
| | | | llvm-svn: 59009
* Use getTargetConstant instead of getConstant for nodes that should not be ↵Dan Gohman2008-11-051-8/+8
| | | | | | | | visited by isel and potentially forced into registers. llvm-svn: 58747
* Shift amounts should have the type given byDuncan Sands2008-10-301-5/+5
| | | | | | getShiftAmountTy (i32 in the case of CellSPU). llvm-svn: 58449
* Resolve bug 2947: vararg-marked functions must spill registers R3-R79 to stackScott Michel2008-10-301-112/+65
| | | | | | | | | so that va_start/va_arg/et.al. will walk arguments correctly for Cell SPU. N.B.: Because neither clang nor llvm-gcc-4.2 can be built for CellSPU, this is still unexorcised code. llvm-svn: 58415
* Teach DAGCombine to fold constant offsets into GlobalAddress nodes,Dan Gohman2008-10-181-0/+6
| | | | | | | | | | | | | | | | | | | | | | and add a TargetLowering hook for it to use to determine when this is legal (i.e. not in PIC mode, etc.) This allows instruction selection to emit folded constant offsets in more cases, such as the included testcase, eliminating the need for explicit arithmetic instructions. This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp that attempted to achieve the same effect, but wasn't as effective. Also, fix handling of offsets in GlobalAddressSDNodes in several places, including changing GlobalAddressSDNode's offset from int to int64_t. The Mips, Alpha, Sparc, and CellSPU targets appear to be unaware of GlobalAddress offsets currently, so set the hook to false on those targets. llvm-svn: 57748
* Rename LoadX to LoadExt.Evan Cheng2008-10-141-9/+9
| | | | llvm-svn: 57526
* Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's asChris Lattner2008-10-111-5/+4
| | | | | | | parameters instead of raw Constants. This prevents the constants from being selected by the isel pass, fixing PR2735. llvm-svn: 57385
* Rename ConstantSDNode's getSignExtended to getSExtValue, forDan Gohman2008-09-261-2/+2
| | | | | | | consistancy with ConstantInt, and re-implement it in terms of ConstantInt's getSExtValue. llvm-svn: 56700
* Properly handle 'm' inline asm constraints. If a GV is being selected for ↵Evan Cheng2008-09-241-1/+3
| | | | | | the addressing mode, it requires the same logic for PIC relative addressing, etc. llvm-svn: 56526
* Make log, log2, log10, exp, exp2 use Expand byDale Johannesen2008-09-221-10/+0
| | | | | | default. llvm-svn: 56471
* Reverting r56249. On further investigation, this functionality isn't needed.Bill Wendling2008-09-161-8/+7
| | | | | | Apologies for the thrashing. llvm-svn: 56251
* - Change "ExternalSymbolSDNode" to "SymbolSDNode".Bill Wendling2008-09-161-7/+8
| | | | | | | | | | - Add linkage to SymbolSDNode (default to external). - Change ISD::ExternalSymbol to ISD::Symbol. - Change ISD::TargetExternalSymbol to ISD::TargetSymbol These changes pave the way to allowing SymbolSDNodes with non-external linkage. llvm-svn: 56249
* Define CallSDNode, an SDNode subclass for use with ISD::CALL.Dan Gohman2008-09-131-11/+12
| | | | | | | | | | | | | Currently it just holds the calling convention and flags for isVarArgs and isTailCall. And it has several utility methods, which eliminate magic 5+2*i and similar index computations in several places. CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle nodes that are not CSE'd gracefully. llvm-svn: 56183
* Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman2008-09-121-41/+51
| | | | | | | with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
* Add intrinsics for log, log2, log10, exp, exp2.Dale Johannesen2008-09-041-0/+10
| | | | | | No functional change (and no FE change to generate them). llvm-svn: 55753
* fix a bunch of 80-col violationsGabor Greif2008-08-311-13/+29
| | | | llvm-svn: 55588
* Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTRBill Wendling2008-08-311-3/+7
| | | | | | | | instructions in CellSPU as "Expand" so that they won't be generated. I added a "FIXME" so that this hack can be addressed and reverted once ISD::ROTR is supported in the .td files. llvm-svn: 55582
* erect abstraction boundaries for accessing SDValue members, rename Val -> ↵Gabor Greif2008-08-281-35/+35
| | | | | | Node to reflect semantics llvm-svn: 55504
* disallow direct access to SDValue::ResNo, provide a getter insteadGabor Greif2008-08-261-1/+1
| | | | llvm-svn: 55394
* Fix broken CellSPU lowering, re-instate braces in LegalizeNate Begeman2008-07-291-2/+3
| | | | llvm-svn: 54168
* Rename SDOperand to SDValue.Dan Gohman2008-07-271-288/+288
| | | | llvm-svn: 54128
* Somehow, custom lowering of i64 multiplications got dropped along the way.Scott Michel2008-07-161-104/+105
| | | | llvm-svn: 53689
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