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path: root/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
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* Added invariant field to the DAG.getLoad method and changed all calls.Pete Cooper2011-11-081-5/+8
| | | | | | When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses llvm-svn: 144100
* Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there wasNadav Rotem2011-10-161-3/+5
| | | | | | no pattern. llvm-svn: 142130
* The CELL backend cannot select patterns for vector trunc-store and shl on ↵Nadav Rotem2011-10-151-0/+9
| | | | | | v2i64; CellSPU/shift_ops.ll fails when promoting elements. llvm-svn: 142081
* Set operation actions to legal types only.Nadav Rotem2011-10-041-8/+9
| | | | llvm-svn: 141075
* Operations should be custom lowered only if their type is legal.Nadav Rotem2011-10-041-6/+8
| | | | | Test: CellSPU/v2i32.ll when running with -promote-elements llvm-svn: 141074
* Add codegen support for vector select (in the IR this means a selectDuncan Sands2011-09-061-1/+2
| | | | | | | | | | | | with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. llvm-svn: 139159
* Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands2011-08-121-0/+1
| | | | | | when building with assertions disabled. llvm-svn: 137460
* Code generation for 'fence' instruction.Eli Friedman2011-07-271-0/+1
| | | | llvm-svn: 136283
* land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner2011-07-181-4/+4
| | | | llvm-svn: 135375
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-1/+0
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* Add an intrinsic and codegen support for fused multiply-accumulate. The intentCameron Zwarich2011-07-081-0/+3
| | | | | | is to use this for architectures that have a native FMA instruction. llvm-svn: 134742
* Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher2011-06-081-8/+8
| | | | | | | | No functional change. Part of PR6965 llvm-svn: 132763
* Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher2011-06-021-2/+2
| | | | | | Part of rdar://9119939 llvm-svn: 132510
* Use the correct register class for Cell varargs spilling. This fixes all of theCameron Zwarich2011-05-191-1/+1
| | | | | | verifier failures in the CodeGen/CellSPU tests. llvm-svn: 131631
* Make the logic for determining function alignment more explicit. No ↵Eli Friedman2011-05-061-5/+2
| | | | | | functionality change. llvm-svn: 131012
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Allow targets to specify a the type of the RHS of a shift parameterized on ↵Owen Anderson2011-02-251-3/+2
| | | | | | the type of the LHS. llvm-svn: 126518
* Revert r124611 - "Keep track of incoming argument's location while emitting ↵Devang Patel2011-02-211-1/+1
| | | | | | | | | | | LiveIns." In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body. This requires some coordination with debugger to get this working. - The debugger needs to be aware of prolog_end attribute attached with line table entries. - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+) llvm-svn: 126155
* Keep track of incoming argument's location while emitting LiveIns.Devang Patel2011-01-311-1/+1
| | | | llvm-svn: 124611
* Allow sign-extending of i8 and i16 to i128 on SPU. Kalle Raiskila2011-01-201-0/+6
| | | | llvm-svn: 123912
* Remove unused variables found by gcc-4.6's -Wunused-but-set-variable.Jeffrey Yasskin2011-01-181-9/+0
| | | | llvm-svn: 123707
* Don't crash SPU BE with memory accesses with big alignmnet.Kalle Raiskila2011-01-171-4/+4
| | | | llvm-svn: 123620
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-101-7/+6
| | | | | | and fixes here and there. llvm-svn: 123170
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-1/+1
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* Use i8 as SETCC result type for i1 in SPU.Kalle Raiskila2010-11-241-4/+14
| | | | llvm-svn: 120092
* Division by pow-of-2 is not cheap on SPU, do it with Kalle Raiskila2010-11-231-2/+0
| | | | | | shifts. llvm-svn: 120022
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-231-92/+92
| | | | llvm-svn: 119990
* Fix a bug with extractelement on SPU.Kalle Raiskila2010-11-221-1/+1
| | | | | | | In the attached testcase, the element was never extracted (missing rotate). llvm-svn: 119973
* Improve code layout, mostly indentation. Kalle Raiskila2010-11-151-166/+150
| | | | | | No functionality change. llvm-svn: 119142
* Fix memory access lowering on SPU, addingKalle Raiskila2010-11-121-102/+219
| | | | | | | | | | | | support for the case where alignment<value size. These cases were silently miscompiled before this patch. Now they are overly verbose -especially storing is- and any front-end should still avoid misaligned memory accesses as much as possible. The bit juggling algorithm added here probably has some room for improvement still. llvm-svn: 118889
* Simplify uses of MVT and EVT. An MVT can be compared directlyDuncan Sands2010-11-031-1/+1
| | | | | | | with a SimpleValueType, while an EVT supports equality and inequality comparisons with SimpleValueType. llvm-svn: 118169
* Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson2010-10-291-0/+33
| | | | | | basic logic, added initial platform support. llvm-svn: 117667
* Improve lowering of sext to i128 on SPU.Kalle Raiskila2010-10-181-2/+7
| | | | | | | | The old algorithm inserted a 'rotqmbyi' instruction which was both redundant and wrong - it made shufb select bytes from the wrong end of the input quad. llvm-svn: 116701
* Implement two virtual functions in SPUTargetLowering.Kalle Raiskila2010-10-071-0/+26
| | | | | | | | | | Before the implementation of isLegalAddressingMode, some rare cases of code were miscompiled if optimized with the LoopStrengthReduce pass. It is unclear (to me) if LSR is "allowed" to produce wrong code with a bad TargetLowering, or if the bug is elsewhere and this patch just hides it. llvm-svn: 115919
* update a bunch of code to use the MachinePointerInfo version of getStore.Chris Lattner2010-09-211-3/+4
| | | | llvm-svn: 114461
* it's more elegant to put the "getConstantPool" andChris Lattner2010-09-211-3/+4
| | | | | | | | "getFixedStack" on the MachinePointerInfo class. While this isn't the problem I'm setting out to solve, it is the right way to eliminate PseudoSourceValue, so lets go with it. llvm-svn: 114406
* Silence compiler warning.Kalle Raiskila2010-09-091-1/+1
| | | | llvm-svn: 113478
* Fix CellSPU vector shuffles, again.Kalle Raiskila2010-09-081-7/+7
| | | | | | Some cases of lowering to rotate were miscompiled. llvm-svn: 113355
* Fix lowering of INSERT_VECTOR_ELT in SPU. Kalle Raiskila2010-08-291-3/+4
| | | | | | The IDX was treated as byte index, not element index. llvm-svn: 112422
* Fix SPU BE to use all the available return registers.Kalle Raiskila2010-08-241-34/+16
| | | | | | llc used to assert on the added testcase. llvm-svn: 111911
* Remove some dead code from SPU BE that remainedKalle Raiskila2010-08-241-18/+6
| | | | | | from 64bit vector support. llvm-svn: 111910
* Fix a bug with insertelement on SPU. Kalle Raiskila2010-08-181-6/+11
| | | | | | | The previous algorithm in LowerVECTOR_SHUFFLE didn't check all requirements for "monotonic" shuffles. llvm-svn: 111361
* Remove all traces of v2[i,f]32 on SPU. Kalle Raiskila2010-08-181-27/+0
| | | | | | | | The "half vectors" are now widened to full size by the legalizer. The only exception is in parameter passing, where half vectors are expanded. This causes changes to some dejagnu tests. llvm-svn: 111360
* Have SPU handle halfvec stores aligned by 8 bytes.Kalle Raiskila2010-08-091-9/+26
| | | | llvm-svn: 110576
* Make SPU backend handle insertelement and Kalle Raiskila2010-08-041-1/+4
| | | | | | store for "half vectors" llvm-svn: 110198
* More SPU v2f32 stuff added: insertelement and shuffle.Kalle Raiskila2010-08-021-0/+1
| | | | llvm-svn: 110038
* Add preliminary v2f32 support for SPU. Like with v2i32, we justKalle Raiskila2010-08-021-0/+2
| | | | | | | | duplicate the instructions and operate on half vectors. Also reorder code in SPUInstrInfo.td for better coherency. llvm-svn: 110037
* Add preliminary v2i32 support for SPU backend. As there are noKalle Raiskila2010-08-021-3/+16
| | | | | | | | | | such registers in SPU, this support boils down to "emulating" them by duplicating instructions on the general purpose registers. This adds the most basic operations on v2i32: passing parameters, addition, subtraction, multiplication and a few others. llvm-svn: 110035
* Switch SPU calling convention (function arguments) Kalle Raiskila2010-07-081-12/+40
| | | | | | to a Tablegen implementation. llvm-svn: 107913
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-071-2/+4
| | | | | | code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
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