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* fix warning in release-asserts mode and spelling of assert.Chris Lattner2009-01-211-3/+2
| | | | llvm-svn: 62699
* Add the private linkage.Rafael Espindola2009-01-151-3/+4
| | | | llvm-svn: 62279
* Rename getABITypeSize to getTypePaddedSize, asDuncan Sands2009-01-121-1/+1
| | | | | | suggested by Chris. llvm-svn: 62099
* Removed trailing whitespace from Makefiles.Misha Brukman2009-01-091-1/+1
| | | | llvm-svn: 61991
* Convert DwarfWriter into a pass.Devang Patel2009-01-081-7/+9
| | | | | | Now Users request DwarfWriter through getAnalysisUsage() instead of creating an instance of DwarfWriter object directly. llvm-svn: 61955
* - Remove Tilmann's custom truncate lowering: it completely hosed overScott Michel2008-12-271-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | DAGcombine's ability to find reasons to remove truncates when they were not needed. Consequently, the CellSPU backend would produce correct, but _really slow and horrible_, code. Replaced with instruction sequences that do the equivalent truncation in SPUInstrInfo.td. - Re-examine how unaligned loads and stores work. Generated unaligned load code has been tested on the CellSPU hardware; see the i32operations.c and i64operations.c in CodeGen/CellSPU/useful-harnesses. (While they may be toy test code, it does prove that some real world code does compile correctly.) - Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc fault because i64 ult is not yet implemented.) - Added i64 eq and neq for setcc and select/setcc; started new instruction information file for them in SPU64InstrInfo.td. Additional i64 operations should be added to this file and not to SPUInstrInfo.td. llvm-svn: 61447
* CellSPU:Scott Michel2008-12-101-0/+12
| | | | | | | | | - Fix bug 3185, with misc other cleanups. - Needed to implement SPUInstrInfo::InsertBranch(). CAUTION: Not sure what gets or needs to get passed to InsertBranch() to insert a conditional branch. This will abort for now until a good test case shows up. llvm-svn: 60811
* CellSPU: Fix bug 3055Scott Michel2008-12-041-1/+0
| | | | | | | | | - Add v4f32, v2f64 to LowerVECTOR_SHUFFLE - Look for vector rotate in shuffle elements, generate a vector rotate instead of a full-blown shuffle when opportunity presents itself. - Generate larger test harness and fix a few interesting but obscure bugs. llvm-svn: 60552
* CellSPU:Scott Michel2008-11-241-1/+1
| | | | | | | | | | (a) Improve the extract element code: there's no need to do gymnastics with rotates into the preferred slot if a shuffle will do the same thing. (b) Rename a couple of SPUISD pseudo-instructions for readability and better semantic correspondence. (c) Fix i64 sign/any/zero extension lowering. llvm-svn: 59965
* CellSPU: Custom lower truncating stores of i8 to i1 (should not have beenScott Michel2008-11-201-2/+3
| | | | | | promote), fix signed conversion of indexed offsets. llvm-svn: 59707
* CMake: corrected library target name for dependency: LLVMCellSPU ->Oscar Fuentes2008-11-081-1/+1
| | | | | | LLVMCellSPUCodeGen. llvm-svn: 58925
* CMake: Reflected changes on the CellSPU target build. May require aOscar Fuentes2008-11-081-0/+12
| | | | | | clean start. llvm-svn: 58924
* Fixed a pasto.Oscar Fuentes2008-11-081-1/+2
| | | | llvm-svn: 58923
* CellSPU: Bring SPU's assembly printer more in-line with current LLVM codeScott Michel2008-11-082-0/+622
structure. Assembly printer now outputs the correct section for strings. llvm-svn: 58921
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