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* [AVR] Enable generation of the TableGen assembly writer tablesDylan McKay2016-10-101-2/+3
| | | | | | | This also changes the order of the statements in CMakeLists.txt to be alphabetical. llvm-svn: 283711
* Move the global variables representing each Target behind accessor functionMehdi Amini2016-10-096-17/+20
| | | | | | | | This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
* [AVR] Add backend dependencies to MCTargetDesc/LLVMBuild.txtDylan McKay2016-10-081-1/+1
| | | | llvm-svn: 283642
* Fix incorrect assertion in AVRFrameLowering.cppDylan McKay2016-10-081-1/+2
| | | | | | This wasn't looking at the right instruction, and would always fail. llvm-svn: 283640
* [AVR] Don't worry about call frame size when initializing frame pointerDylan McKay2016-10-081-3/+2
| | | | | | | | | | | | | We previously only used the frame pointer if the frame pointer was too big. This was to work around a bug (described in this old commit) https://sourceforge.net/p/avr-llvm/code/204/tree//llvm/trunk/AVR/AVRFrameLowering.cpp?diff=50d64d912718465cb887d17a:203 I mistakenly invered the condition assuming it was a typo. I am now removing it because it doesn't seem to be a problem anymore (plus it's a dirty hack). llvm-svn: 283639
* [AVR] Don't shadow container while iterating in range-based loopDylan McKay2016-10-081-2/+4
| | | | | | This works on clang, but fails on GCC 4.6 llvm-svn: 283638
* [AVR] Use references rather than pointers in AVRISelLoweringDylan McKay2016-10-081-2/+2
| | | | llvm-svn: 283636
* Allow a maximum of 64 bits to be returned in registersDylan McKay2016-10-081-0/+8
| | | | | | | | The rest spills to the stack Authored by Jake Goulding llvm-svn: 283635
* [AVR] Expand MULHS for all typesDylan McKay2016-10-081-0/+3
| | | | | | | | | | Once MULHS was expanded, this exposed an issue where the condition register was thought to be 16-bit. This caused an attempt to copy a 16-bit register to an 8-bit register. Authored by Jake Goulding llvm-svn: 283634
* [AVR] Add the 'SoftFail' field to all instruction formatsDylan McKay2016-10-081-0/+2
| | | | | | This will be used in the future for disassembly. llvm-svn: 283630
* [AVR] Set up the instruction printer and the assembly backendDylan McKay2016-10-081-0/+19
| | | | llvm-svn: 283629
* [AVR] Add dependencies to AVR libraries in AVRCodeGenDylan McKay2016-10-081-1/+2
| | | | llvm-svn: 283628
* [AVR] Add missing subdirectories to LLVMBuildDylan McKay2016-10-081-1/+1
| | | | llvm-svn: 283627
* [AVR] Add the assembly printerDylan McKay2016-10-082-0/+183
| | | | | | | | | | | | Summary: This adds the AVRAsmPrinter class. Reviewers: arsenm, kparzysz Subscribers: llvm-commits, wdng, beanz, japaric, mgorny Differential Revision: https://reviews.llvm.org/D25271 llvm-svn: 283623
* [AVR] Add the AVRMCInstLower classDylan McKay2016-10-073-0/+144
| | | | | | | | | | | | | | Summary: This class deals with the lowering of CodeGen `MachineInstr` objects to MC `MCInst` objects. Reviewers: kparzysz, arsenm Subscribers: wdng, beanz, japaric, mgorny Differential Revision: https://reviews.llvm.org/D25269 llvm-svn: 283522
* [AVR] Don't select 'MOVW' instructions when they are not supportedDylan McKay2016-10-051-15/+41
| | | | | | | We have a subtarget feature which we were ignoring, which was causing us to generate unsupported instructions for some older chips. llvm-svn: 283317
* [AVR] Add AVRRegisterInfo::splitReg functionDylan McKay2016-10-052-2/+14
| | | | | | | No tests are included just yet - this is used from the pseudo instruction expander pass, which hasn't been pulled in-tree yet. llvm-svn: 283316
* [AVR] Update return type of dynamic alloca passDylan McKay2016-10-051-2/+2
| | | | | | It was recently changed from 'const char*' to StringRef llvm-svn: 283312
* [AVR] Add the AVR frame lowering codeDylan McKay2016-10-052-0/+538
| | | | | | | | | | | | Summary: This allows AVR to lower frames into assembly code. Reviewers: arsenm, kparzysz Subscribers: japaric, wdng, beanz, mgorny Differential Revision: https://reviews.llvm.org/D25032 llvm-svn: 283311
* [AVR] Split all of the AVR device definitions into a separate fileDylan McKay2016-10-052-487/+493
| | | | | | | We have ~500 lines of subtarget feature definitions, they don't belong in our main TableGen file. llvm-svn: 283310
* [AVR] Enable the instruction printer in the target definitionDylan McKay2016-10-051-5/+5
| | | | llvm-svn: 283309
* [AVR] Add definitions for the ATTiny102 and ATtiny104 chipsDylan McKay2016-10-051-0/+2
| | | | llvm-svn: 283308
* [AVR] Add the machine code backendDylan McKay2016-10-053-0/+552
| | | | | | | | | | | | | | Summary: This adds the AVR machine code backend (`AVRAsmBackend.cpp`). This will allow us to generate machine code from assembled AVR instructions. Reviewers: arsenm, kparzysz Subscribers: modocache, japaric, wdng, beanz, mgorny Differential Revision: https://reviews.llvm.org/D25029 llvm-svn: 283297
* [AVR] Add the ELF object file writerDylan McKay2016-09-302-0/+128
| | | | | | | | | | | | Summary: This adds the ELF32 writer for AVR. Reviewers: kparzysz Subscribers: beanz, mgorny Differential Revision: https://reviews.llvm.org/D25031 llvm-svn: 282856
* [AVR] Add the assembly instruction printerDylan McKay2016-09-306-2/+260
| | | | | | | | | | | | | | | | | Summary: This change adds the AVR assembly instruction printer. No tests are included in this patch. I have left them downstream so we can add them once `llc` successfully runs (there's very few components left to upstream until this). Reviewers: arsenm, kparzysz Subscribers: wdng, beanz, mgorny Differential Revision: https://reviews.llvm.org/D25028 llvm-svn: 282854
* Revert "[AVR] Add instruction selection lowering code"Dylan McKay2016-09-293-1954/+2
| | | | | | I accidentally comitted it. llvm-svn: 282712
* [AVR] Add instruction selection lowering codeDylan McKay2016-09-293-2/+1954
| | | | | | | | | | | | Summary: This adds AVRISelLowering.cpp Reviewers: kparzysz, arsenm Subscribers: wdng, beanz, mgorny Differential Revision: https://reviews.llvm.org/D25034 llvm-svn: 282711
* [AVR] Rename the builtin calling convention namesDylan McKay2016-09-281-3/+3
| | | | | | 'BUILTIN' is clearer than 'RT' in this context. llvm-svn: 282602
* [AVR] Import the LLVM namespace inside AVRMCTargetDesc.cppDylan McKay2016-09-281-0/+2
| | | | llvm-svn: 282598
* [AVR] Add AVRMCTargetDesc.cppDylan McKay2016-09-283-4/+97
| | | | | | | | | | | | | | Summary: This adds the AVRMCTargetDesc file in tree. It allows creation of the core classes used in the backend. Reviewers: arsenm, kparzysz Subscribers: wdng, beanz, mgorny Differential Revision: https://reviews.llvm.org/D25023 llvm-svn: 282597
* [AVR] Update the signature of createAVRAsmBackendDylan McKay2016-09-281-1/+3
| | | | | | It has been recently changed to also take a MCTargetOptions structure. llvm-svn: 282594
* [AVR] Enable the assembly parserDylan McKay2016-09-282-15/+18
| | | | | | | | We very recently landed the code. This commit enables the parser. It also adds a missing include to AVRAsmParser.cpp llvm-svn: 282593
* [AVR] Merge most recent changes to AVRInstrInfo.tdDylan McKay2016-09-281-21/+85
| | | | | | | | | This adds two new things: - Operand types per fixup - Atomic pseudo operations llvm-svn: 282588
* [AVR] Update the data layoutDylan McKay2016-09-281-1/+3
| | | | | | | | | | | | | | | The previous data layout caused issues when dealing with atomics. Foe example, it is illegal to load a 16-bit value with less than 16-bits of alignment. This changes the data layout so that all types are aligned by at least their own width. Interestingly, this also _slightly_ decreased register pressure in some cases. llvm-svn: 282587
* [AVR] Add assembly parserDylan McKay2016-09-285-1/+658
| | | | | | | | | | | | Summary: This patch adds the AVRAsmParser library. Reviewers: arsenm, kparzysz Subscribers: wdng, beanz, mgorny, kparzysz, simoncook, jtbandes, llvm-commits Differential Revision: https://reviews.llvm.org/D20046 llvm-svn: 282584
* [AVR] Add AVRMCExprDylan McKay2016-09-264-0/+427
| | | | | | | | | | | | Summary: This adds the AVRMCExpr headers and implementation. Reviewers: arsenm, ruiu, grosbach, kparzysz Subscribers: wdng, beanz, mgorny, kparzysz, jtbandes, llvm-commits Differential Revision: https://reviews.llvm.org/D20503 llvm-svn: 282397
* [AVR] Update signature of AVRTargetObjectFile::SelectSectionForGlobalDylan McKay2016-09-242-3/+3
| | | | | | It was changed recently, and was breaking compilation of the backend. llvm-svn: 282329
* Finish renaming remaining analyzeBranch functionsMatt Arsenault2016-09-142-4/+4
| | | | llvm-svn: 281535
* Make analyzeBranch family of instruction names consistentMatt Arsenault2016-09-142-3/+3
| | | | | | | analyzeBranch was renamed to use lowercase first, rename the related set to match. llvm-svn: 281506
* AArch64: Use TTI branch functions in branch relaxationMatt Arsenault2016-09-142-4/+12
| | | | | | | | | The main change is to return the code size from InsertBranch/RemoveBranch. Patch mostly by Tim Northover llvm-svn: 281505
* Replace "fallthrough" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-171-1/+1
| | | | | | | This is a mechanical change of comments in switches like fallthrough, fall-through, or fall-thru to use the LLVM_FALLTHROUGH macro instead. llvm-svn: 278902
* [AVR] Fix compile errorsJob Noorman2016-08-162-5/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D23450 llvm-svn: 278784
* TargetInstrInfo: add virtual function getInstSizeInBytesSjoerd Meijer2016-07-291-1/+1
| | | | | | | | | This adds a target hook getInstSizeInBytes to TargetInstrInfo that a lot of subclasses already implement. Differential Revision: https://reviews.llvm.org/D22885 llvm-svn: 277126
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-282-5/+5
| | | | | | | getFrameInfo() never returns nullptr so we should use a reference instead of a pointer. llvm-svn: 277017
* TargetInstrInfo: rename GetInstSizeInBytes to getInstSizeInBytes. NFCSjoerd Meijer2016-07-282-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D22925 llvm-svn: 276997
* Rename AnalyzeBranch* to analyzeBranch*.Jacques Pienaar2016-07-152-2/+2
| | | | | | | | | | | | Summary: NFC. Rename AnalyzeBranch/AnalyzeBranchPredicate to analyzeBranch/analyzeBranchPredicate to follow LLVM coding style and be consistent with TargetInstrInfo's analyzeCompare and analyzeSelect. Reviewers: tstellarAMD, mcrosier Subscribers: mcrosier, jholewinski, jfb, arsenm, dschuff, jyknight, dsanders, nemanjai Differential Revision: https://reviews.llvm.org/D22409 llvm-svn: 275564
* CodeGen: Use MachineInstr& in TargetLowering, NFCDuncan P. N. Exon Smith2016-06-301-1/+1
| | | | | | | | | | | | | This is a mechanical change to make TargetLowering API take MachineInstr& (instead of MachineInstr*), since the argument is expected to be a valid MachineInstr. In one case, changed a parameter from MachineInstr* to MachineBasicBlock::iterator, since it was used as an insertion point. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. llvm-svn: 274287
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-302-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. llvm-svn: 274189
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-123-10/+10
| | | | | | | | This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. llvm-svn: 272512
* [AVR] Add AVRMCAsmInfoDylan McKay2016-05-213-0/+60
| | | | llvm-svn: 270302
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