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* [AVR] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1110-36/+6
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360493
* [AsmPrinter] refactor to support %c w/ GlobalAddress'Nick Desaulniers2019-04-261-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Targets like ARM, MSP430, PPC, and SystemZ have complex behavior when printing the address of a MachineOperand::MO_GlobalAddress. Move that handling into a new overriden method in each base class. A virtual method was added to the base class for handling the generic case. Refactors a few subclasses to support the target independent %a, %c, and %n. The patch also contains small cleanups for AVRAsmPrinter and SystemZAsmPrinter. It seems that NVPTXTargetLowering is possibly missing some logic to transform GlobalAddressSDNodes for TargetLowering::LowerAsmOperandForConstraint to handle with "i" extended inline assembly asm constraints. Fixes: - https://bugs.llvm.org/show_bug.cgi?id=41402 - https://github.com/ClangBuiltLinux/linux/issues/449 Reviewers: echristo, void Reviewed By: void Subscribers: void, craig.topper, jholewinski, dschuff, jyknight, dylanmckay, sdardis, nemanjai, javed.absar, sbc100, jgravelle-google, eraman, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, jrtc27, atanasyan, jsji, llvm-commits, kees, tpimh, nathanchance, peter.smith, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D60887 llvm-svn: 359337
* [AsmPrinter] refactor to remove remove AsmVariant. NFCNick Desaulniers2019-04-101-9/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: The InlineAsm::AsmDialect is only required for X86; no architecture makes use of it and as such it gets passed around between arch-specific and general code while being unused for all architectures but X86. Since the AsmDialect is queried from a MachineInstr, which we also pass around, remove the additional AsmDialect parameter and query for it deep in the X86AsmPrinter only when needed/as late as possible. This refactor should help later planned refactors to AsmPrinter, as this difference in the X86AsmPrinter makes it harder to make AsmPrinter more generic. Reviewers: craig.topper Subscribers: jholewinski, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, sbc100, jgravelle-google, eraman, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, llvm-commits, peter.smith, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D60488 llvm-svn: 358101
* [AVR] Fix a typo - 's/analisys/analysis'Dylan McKay2019-02-131-1/+1
| | | | llvm-svn: 353987
* Implementation of asm-goto support in LLVMCraig Topper2019-02-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | This patch accompanies the RFC posted here: http://lists.llvm.org/pipermail/llvm-dev/2018-October/127239.html This patch adds a new CallBr IR instruction to support asm-goto inline assembly like gcc as used by the linux kernel. This instruction is both a call instruction and a terminator instruction with multiple successors. Only inline assembly usage is supported today. This also adds a new INLINEASM_BR opcode to SelectionDAG and MachineIR to represent an INLINEASM block that is also considered a terminator instruction. There will likely be more bug fixes and optimizations to follow this, but we felt it had reached a point where we would like to switch to an incremental development model. Patch by Craig Topper, Alexander Ivchenko, Mikhail Dvoretckii Differential Revision: https://reviews.llvm.org/D53765 llvm-svn: 353563
* [AVR] Insert unconditional branch when inserting MBBs between blocks with ↵Dylan McKay2019-01-211-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | fallthrough This updates the AVR Select8/Select16 expansion code so that, when inserting the two basic blocks for true and false conditions, any existing fallthrough on the previous block is preserved. Prior to this patch, if the block before the Select pseudo fell through to the subsequent block, two new basic blocks would be inserted at the prior fallthrough point, changing the fallthrough destination. The predecessor or successor lists were not updated, causing the BranchFolding pass at -O1 and above the rearrange basic blocks, causing an infinite loop. Not to mention the unconditional fallthrough to the true block is incorrect in of itself. This patch modifies the Select8/16 expansion so that, if inserting true and false basic blocks at a fallthrough point, the implicit branch is preserved by means of an explicit, unconditional branch to the previous fallthrough destination. Thanks to Carl Peto for reporting this bug. This fixes avr-rust bug https://github.com/avr-rust/rust/issues/123. llvm-svn: 351721
* [AVR] Enable emission of debug informationDylan McKay2019-01-211-0/+1
| | | | | | | | | | | | | | Prior to this, the code was missing AVR-specific relocation logic in RelocVisitor.h. This patch teaches RelocVisitor about R_AVR_16 and R_AVR_32. Debug information is emitted in the final object file, and understood by 'avr-readelf --debug-dump' from AVR-GCC. llvm-dwarfdump is yet to understand how to dump AVR DWARF symbols. llvm-svn: 351720
* Revert "[AVR] Insert unconditional branch when inserting MBBs between blocks ↵Dylan McKay2019-01-211-9/+0
| | | | | | | | | | | | with fallthrough" This reverts commit r351718. Carl pointed out that the unit test could be improved. This patch will be recommitted once the test is made more resilient. llvm-svn: 351719
* [AVR] Insert unconditional branch when inserting MBBs between blocks with ↵Dylan McKay2019-01-211-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | fallthrough This updates the AVR Select8/Select16 expansion code so that, when inserting the two basic blocks for true and false conditions, any existing fallthrough on the previous block is preserved. Prior to this patch, if the block before the Select pseudo fell through to the subsequent block, two new basic blocks would be inserted at the prior fallthrough point, changing the fallthrough destination. The predecessor or successor lists were not updated, causing the BranchFolding pass at -O1 and above the rearrange basic blocks, causing an infinite loop. Not to mention the unconditional fallthrough to the true block is incorrect in of itself. This patch modifies the Select8/16 expansion so that, if inserting true and false basic blocks at a fallthrough point, the implicit branch is preserved by means of an explicit, unconditional branch to the previous fallthrough destination. Thanks to Carl Peto for reporting this bug. This fixes avr-rust bug https://github.com/avr-rust/rust/issues/123. llvm-svn: 351718
* [AVR] Replace two references to ARM's 't2_so_imm' type commentsDylan McKay2019-01-201-2/+2
| | | | | | | | | | | These were originally introduced in a copy-paste committed in r351526. The reference to 't2_so_imm' have been updated to 'imm_com8' so the comment is now accurate. Thanks to Eli Friedman for noticing this. llvm-svn: 351674
* [AVR] Fix codegen bug in 16-bit loadsDylan McKay2019-01-202-8/+5
| | | | | | | | | | | | | | | | | | | | | | | | Prior to this patch, the AVR::LDWRdPtr instruction was always lowered to instructions of this pattern: ld $GPR8, [PTR:XYZ]+ ld $GPR8, [PTR]+1 This has a problem; the [PTR] is incremented in-place once, but never decremented. Future uses of the same pointer will use the now clobbered value, leading to the pointer being incorrect by an offset of one. This patch modifies the expansion code of the LDWRdPtr pseudo instruction so that the pointer variable is not silently clobbered in future uses in the same live range. Bug first reported by Keshav Kini. Patch by Kaushik Phatak. llvm-svn: 351673
* Revert "[AVR] Fix codegen bug in 16-bit loads"Dylan McKay2019-01-201-5/+5
| | | | | | | | | | | This reverts commit r351544. In that commit, I had mistakenly misattributed the issue submitter as the patch author, Kaushik Phatak. The patch will be recommitted immediately with the correct attribution. llvm-svn: 351672
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-1956-224/+168
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [AVR] Fix codegen bug in 16-bit loadsDylan McKay2019-01-181-5/+5
| | | | | | | | | | | | | | | | | | | | | | Prior to this patch, the AVR::LDWRdPtr instruction was always lowered to instructions of this pattern: ld $GPR8, [PTR:XYZ]+ ld $GPR8, [PTR]+1 This has a problem; the [PTR] is incremented in-place once, but never decremented. Future uses of the same pointer will use the now clobbered value, leading to the pointer being incorrect by an offset of one. This patch modifies the expansion code of the LDWRdPtr pseudo instruction so that the pointer variable is not silently clobbered in future uses in the same live range. Patch by Keshav Kini. llvm-svn: 351544
* [AVR] Rewrite the CBRRdK instruction as an alias of ANDIRdKDylan McKay2019-01-182-21/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CBR instruction is just an ANDI instruction with the immediate complemented. Because of this, prior to this change TableGen would warn due to a decoding conflict. This commit fixes the existing compilation warning: =============== [423/492] Building AVRGenDisassemblerTables.inc... Decoding Conflict: 0111............ 01.............. ................ ANDIRdK 0111____________ CBRRdK 0111____________ ================ After this commit, there are no more decoding conflicts in the AVR backend's instruction definitions. Thanks to Eli F for pointing me torward `t2_so_imm_not` as an example of how to perform a complement in an instruction alias. Fixes BugZilla PR38802. llvm-svn: 351526
* [AVR] Expand 8/16-bit multiplication to libcalls on MCUs that don't have ↵Dylan McKay2019-01-184-15/+38
| | | | | | | | | | | | | | | | | hardware MUL This change modifies the LLVM ISel lowering settings so that 8-bit/16-bit multiplication is expanded to calls into the compiler runtime library if the MCU being targeted does not support multiplication in hardware. Before this, MUL instructions would be generated on CPUs like the ATtiny85, triggering a CPU reset due to an illegal instruction at runtime. First raised in https://github.com/avr-rust/rust/issues/124. llvm-svn: 351523
* [Targets] Add errors for tiny and kernel codemodel on targets that don't ↵David Green2018-12-071-8/+2
| | | | | | | | | | | support them Adds fatal errors for any target that does not support the Tiny or Kernel codemodels by rejigging the getEffectiveCodeModel calls. Differential Revision: https://reviews.llvm.org/D50141 llvm-svn: 348585
* [AVR] Silence fallthrough warning. NFC.Nirav Dave2018-12-041-0/+1
| | | | llvm-svn: 348304
* Fix modules build of AVRAsmParser.cppAlexander Richardson2018-11-131-3/+4
| | | | | | | | | | | | | | | | | Summary: Without this change I get the following error: lib/Target/AVR/AVRGenAsmMatcher.inc:1135:1: error: redundant #include of module 'LLVM_Utils.Support.Format' appears within namespace 'llvm' [-Wmodules-import-nested-redundant] Reviewers: dylanmckay Reviewed By: dylanmckay Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53425 llvm-svn: 346750
* [AVR] Fix a backend bug that left extraneous operands after expansionDylan McKay2018-11-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | This patch fixes a bug in the AVR FRMIDX expansion logic. The expansion would leave a leftover operand from the original FRMIDX, but now attached to a MOVWRdRr instruction. The MOVWRdRr instruction did not expect this operand and so LLVM rejected the machine instruction. This would trigger an assertion: Assertion failed: ((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isMetaDataOp) && "Trying to add an operand to a machine instr that is already done!"), function addOperand, file llvm/lib/CodeGen/MachineInstr.cpp Tim fixed this so that now the FRMIDX is expanded correctly into a well-formed MOVWRdRr. Patch by Tim Neumann llvm-svn: 346117
* [AVR] Disallow the LDDWRdPtrQ instruction with Z as the destinationDylan McKay2018-11-052-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an AVR-specific workaround for a limitation of the register allocator that only exposes itself on targets with high register contention like AVR, which only has three pointer registers. The three pointer registers are X, Y, and Z. In most nontrivial functions, Y is reserved for the frame pointer, as per the calling convention. This leaves X and Z. Some instructions, such as LPM ("load program memory"), are only defined for the Z register. Sometimes this just leaves X. When the backend generates a LDDWRdPtrQ instruction with Z as the destination pointer, it usually trips up the register allocator with this error message: LLVM ERROR: ran out of registers during register allocation This patch is a hacky workaround. We ban the LDDWRdPtrQ instruction from ever using the Z register as an operand. This gives the register allocator a bit more space to allocate, fixing the regalloc exhaustion error. Here is a description from the patch author Peter Nimmervoll As far as I understand the problem occurs when LDDWRdPtrQ uses the ptrdispregs register class as target register. This should work, but the allocator can't deal with this for some reason. So from my testing, it seams like (and I might be totally wrong on this) the allocator reserves the Z register for the ICALL instruction and then the register class ptrdispregs only has 1 register left and we can't use Y for source and destination. Removing the Z register from DREGS fixes the problem but removing Y register does not. More information about the bug can be found on the avr-rust issue tracker at https://github.com/avr-rust/rust/issues/37. A bug has raised to track the removal of this workaround and a proper fix; PR39553 at https://bugs.llvm.org/show_bug.cgi?id=39553. Patch by Peter Nimmervoll llvm-svn: 346114
* [AVR] Redefine the 'LSL' instruction as an alias of 'ADD'Dylan McKay2018-09-013-10/+19
| | | | | | The 'LSL Rd' instruction is equivalent to 'ADD Rd, Rd'. llvm-svn: 341278
* [AVR] Redefine the 'SBR' instruction as an aliasDylan McKay2018-09-011-9/+8
| | | | | | | | | | | This fixes a TableGen warning about duplicate bit patterns. SBR === This is an alias of 'ORI Rd, K'. llvm-svn: 341277
* [AVR] Define the TST instruction as an alias of ANDDylan McKay2018-09-011-9/+6
| | | | | | The 'tst Rd' instruction is equivalent to 'and Rd, Rd'. llvm-svn: 341276
* [AVR] Define the ROL instruction as an alias of ADCDylan McKay2018-09-013-11/+15
| | | | | | | | | The 'rol Rd' instruction is equivalent to 'adc Rd'. This caused compile warnings from tablegen because of conflicting bits shared between each instruction. llvm-svn: 341275
* [MI] Change the array of `MachineMemOperand` pointers to beChandler Carruth2018-08-161-26/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a generically extensible collection of extra info attached to a `MachineInstr`. The primary change here is cleaning up the APIs used for setting and manipulating the `MachineMemOperand` pointer arrays so chat we can change how they are allocated. Then we introduce an extra info object that using the trailing object pattern to attach some number of MMOs but also other extra info. The design of this is specifically so that this extra info has a fixed necessary cost (the header tracking what extra info is included) and everything else can be tail allocated. This pattern works especially well with a `BumpPtrAllocator` which we use here. I've also added the basic scaffolding for putting interesting pointers into this, namely pre- and post-instruction symbols. These aren't used anywhere yet, they're just there to ensure I've actually gotten the data structure types correct. I'll flesh out support for these in a subsequent patch (MIR dumping, parsing, the works). Finally, I've included an optimization where we store any single pointer inline in the `MachineInstr` to avoid the allocation overhead. This is expected to be the overwhelmingly most common case and so should avoid any memory usage growth due to slightly less clever / dense allocation when dealing with >1 MMO. This did require several ergonomic improvements to the `PointerSumType` to reasonably support the various usage models. This also has a side effect of freeing up 8 bits within the `MachineInstr` which could be repurposed for something else. The suggested direction here came largely from Hal Finkel. I hope it was worth it. ;] It does hopefully clear a path for subsequent extensions w/o nearly as much leg work. Lots of thanks to Reid and Justin for careful reviews and ideas about how to do all of this. Differential Revision: https://reviews.llvm.org/D50701 llvm-svn: 339940
* [SDAG] Update the AVR backend for the SelectionDAG API changes inChandler Carruth2018-08-151-6/+2
| | | | | | r339740, fixing the build for this target. llvm-svn: 339748
* [AVR] Re-enable expansion of ADDE/ADDC/SUBE/SUBC in ISelDylan McKay2018-07-291-0/+7
| | | | | | | | | This was disabled in r333748, which broke four tests. In the future, these need to be updated to UADDO/ADDCARRY or USUBO/SUBCARRY. llvm-svn: 338212
* [AVR] Document some public functionsDylan McKay2018-07-151-0/+2
| | | | llvm-svn: 337122
* [AVR] Set trackLivenessAfterRegAllocDylan McKay2018-06-111-0/+5
| | | | | | | | | | | | | | | | | This sets trackLivenessAfterRegAlloc on AVRRegisterInfo. Most existing targets set this flag. Without it, specific IR inputs cause LLVM to fail with: Assertion failed: (getParent()->getProperties().hasProperty( MachineFunctionProperties::Property::TracksLiveness) && "Liveness information is accurate"), function livein_begin file MachineBasicBlock.cpp, line 1354. With this commit, this no longer happens. Patch by Peter Nimmervoll. llvm-svn: 334409
* [AVR] Fix build after r334078Alex Bradbury2018-06-072-4/+10
| | | | | | | r334078 added MCSubtargetInfo to fixupNeedsRelaxation and applyFixup. This patch makes the necessary adjustment for the AVR target. llvm-svn: 334202
* MC: Separate creating a generic object writer from creating a target object ↵Peter Collingbourne2018-05-214-12/+9
| | | | | | | | | | | | | writer. NFCI. With this we gain a little flexibility in how the generic object writer is created. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47045 llvm-svn: 332868
* MC: Change MCAsmBackend::writeNopData() to take a raw_ostream instead of an ↵Peter Collingbourne2018-05-212-5/+4
| | | | | | | | | | | | | MCObjectWriter. NFCI. To make this work I needed to add an endianness field to MCAsmBackend so that writeNopData() implementations know which endianness to use. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47035 llvm-svn: 332857
* MC: Change the streamer ctors to take an object writer instead of a stream. ↵Peter Collingbourne2018-05-183-10/+15
| | | | | | | | | | | | | | NFCI. The idea is that a client that wants split dwarf would create a specific kind of object writer that creates two files, and use it to create the streamer. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47050 llvm-svn: 332749
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-142-3/+3
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-091-2/+2
| | | | | | | | | | | | | | | | | | Because we create a new kind of debug instruction, DBG_LABEL, we need to check all passes which use isDebugValue() to check MachineInstr is debug instruction or not. When expelling debug instructions, we should expel both DBG_VALUE and DBG_LABEL. So, I create a new function, isDebugInstr(), in MachineInstr to check whether the MachineInstr is debug instruction or not. This patch has no new test case. I have run regression test and there is no difference in regression test. Differential Revision: https://reviews.llvm.org/D45342 Patch by Hsiangkai Wang. llvm-svn: 331844
* Remove duplicate tablegen lines from AVR target.Nico Weber2018-04-041-6/+2
| | | | | | | | | | They were added in r285274, in what looks like a merge mishap. AVRGenMCCodeEmitter.inc is the only non-dupe tablegen invocation added in that revision. Also sort the tablegen lines to make this easier to spot in the future. llvm-svn: 329178
* [AVR] Lower i128 divisions to runtime library callsDylan McKay2018-03-191-0/+3
| | | | | | | | | | | This patch adds i128 division support by instruction LLVM to lower 128-bit divisions to the __udivmodti4 and __divmodti4 rtlib functions. This also adds test for 64-bit division and 128-bit division. Patch by Peter Nimmervoll. llvm-svn: 327814
* [AVR] Remove the earlyclobber flag from LDDWRdYQDylan McKay2018-03-061-2/+16
| | | | | | | | | | | | | | | | | Before I started maintaining the AVR backend, this instruction never originally used to have an earlyclobber flag. Some time afterwards (years ago), I must've added it back in, not realising that it was left out for a reason. This pseudo instrction exists solely to work around a long standing bug in the register allocator. Before this commit, the LDDWRdYQ pseudo was not actually working around any bug. With the earlyclobber flag removed again, the LDDWRdYQ pseudo now correctly works around PR13375 again. llvm-svn: 326774
* [AVR] Set the program address space in the data layoutDylan McKay2018-02-191-1/+1
| | | | | | | | | | | | This adds the program memory address space setting to the AVR data layout. This setting was very recently added under r325479. At the moment, there are no uses of this setting. In the future, things such as switch lookup tables should reside there. llvm-svn: 325481
* [AVR] Fix a lowering bug in AVRISelLowering.cppDylan McKay2018-02-191-4/+6
| | | | | | | | | | | | | | The parseFunctionArgs() method was directly reading the arguments from a Function object, but is should have used the arguments supplied by the SelectionDAGBuilder. This was causing the lowering code to only lower one argument, not two in some cases. Thanks to @brainlag on GitHub for coming up with the working fix! Patch-by: @brainlag on GitHub llvm-svn: 325474
* [SelectionDAGISel] Add a debug print before call to Select. Adjust where ↵Craig Topper2018-01-261-3/+0
| | | | | | | | | | | | blank lines are printed during isel process to make things more sensibly grouped. Previously some targets printed their own message at the start of Select to indicate what they were selecting. For the targets that didn't, it means there was no print of the root node before any custom handling in the target executed. So if the target did something custom and never called SelectNodeCommon, no print would be made. For the targets that did print a message in Select, if they didn't custom handle a node SelectNodeCommon would reprint the root node before walking the isel table. It seems better to just print the message before the call to Select so all targets behave the same. And then remove the root node printing from SelectNodeCommon and just leave a message that says we're starting the table search. There were also some oddities in blank line behavior. Usually due to a \n after a call to SelectionDAGNode::dump which already inserted a new line. llvm-svn: 323551
* Fix build of WebAssembly and AVR backends after r321692Alex Bradbury2018-01-032-5/+6
| | | | | | | As experimental backends, I didn't have them configured to build in my local build config. llvm-svn: 321696
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-153-5/+5
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* [AVR] Implement some missing code pathsDylan McKay2017-12-112-4/+19
| | | | | | This has been broken since r320009. llvm-svn: 320348
* [AVR] Fix incorrectly-calculated AVRMCExpr evaluationsDylan McKay2017-12-111-12/+9
| | | | | | This has been broken since r320009. llvm-svn: 320347
* Revert and accidentally committed revert commitDylan McKay2017-12-0911-22/+275
| | | | | | This reverts commit r320245. llvm-svn: 320247
* Revert "[AVR] Override ParseDirective"Dylan McKay2017-12-0911-275/+22
| | | | | | This reverts commit 57c16f9267969ebb09d6448607999b4a9f40c418. llvm-svn: 320245
* Relax unaligned access assertion when type is byte alignedDylan McKay2017-12-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This relaxes an assertion inside SelectionDAGBuilder which is overly restrictive on targets which have no concept of alignment (such as AVR). In these architectures, all types are aligned to 8-bits. After this, LLVM will only assert that accesses are aligned on targets which actually require alignment. This patch follows from a discussion on llvm-dev a few months ago http://llvm.1065342.n5.nabble.com/llvm-dev-Unaligned-atomic-load-store-td112815.html Reviewers: bogner, nemanjai, joerg, efriedma Reviewed By: efriedma Subscribers: efriedma, cactus, llvm-commits Differential Revision: https://reviews.llvm.org/D39946 llvm-svn: 320243
* [AVR] Override ParseDirectiveLeslie Zhai2017-12-0711-22/+275
| | | | | | | | | | Reviewers: dylanmckay, kparzysz Reviewed By: dylanmckay Differential Revision: https://reviews.llvm.org/D38029 llvm-svn: 320009
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